blob: e5d285855ec6bca70e7c9884277d69812d58ae66 [file] [log] [blame]
Jon Murphya8590572023-02-23 13:42:52 -07001/* SPDX-License-Identifier: GPL-2.0-or-later */
2
Felix Held00792002024-01-26 14:41:14 +01003#include <amdblocks/acpi.h>
Jon Murphy9a2d0e62023-03-29 17:00:01 -06004#include <amdblocks/acpimmio.h>
Jon Murphya8590572023-02-23 13:42:52 -07005#include <amdblocks/amd_pci_util.h>
Jon Murphy2c4a4d22023-04-06 17:19:14 -06006#include <amdblocks/xhci.h>
Jon Murphya8590572023-02-23 13:42:52 -07007#include <baseboard/variants.h>
Jon Murphy3f348792023-03-29 15:36:01 -06008#include <console/console.h>
Jon Murphy2c4a4d22023-04-06 17:19:14 -06009#include <cpu/x86/smm.h>
Jon Murphya8590572023-02-23 13:42:52 -070010#include <device/device.h>
Jon Murphy1236b332023-03-29 18:51:12 -060011#include <drivers/i2c/tpm/chip.h>
Jon Murphya4564582023-03-29 15:38:19 -060012#include <variant/ec.h>
Jon Murphya8590572023-02-23 13:42:52 -070013
Jon Murphyfb5d1572023-03-29 18:28:42 -060014/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
15 accessed via I/O ports 0xc00/0xc01. */
16
17/*
18 * This controls the device -> IRQ routing.
19 *
20 * Hardcoded IRQs:
21 * 0: timer < soc/amd/common/acpi/lpc.asl
22 * 1: i8042 - Keyboard
23 * 2: cascade
24 * 8: rtc0 <- soc/amd/common/acpi/lpc.asl
25 * 9: acpi <- soc/amd/common/acpi/lpc.asl
26 */
27
Jon Murphya8590572023-02-23 13:42:52 -070028static const struct fch_irq_routing fch_irq_map[] = {
Jon Murphyfb5d1572023-03-29 18:28:42 -060029 { PIRQ_A, 12, PIRQ_NC },
30 { PIRQ_B, 14, PIRQ_NC },
31 { PIRQ_C, 15, PIRQ_NC },
32 { PIRQ_D, 12, PIRQ_NC },
33 { PIRQ_E, 14, PIRQ_NC },
34 { PIRQ_F, 15, PIRQ_NC },
35 { PIRQ_G, 12, PIRQ_NC },
36 { PIRQ_H, 14, PIRQ_NC },
37
38 { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
39 { PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
40 { PIRQ_GPIO, 11, 11 },
41 { PIRQ_I2C0, 10, 10 },
42 { PIRQ_I2C1, 7, 7 },
43 { PIRQ_I2C2, 6, 6 },
44 { PIRQ_I2C3, 5, 5 },
45 { PIRQ_UART0, 4, 4 },
46 { PIRQ_UART1, 3, 3 },
47
48 /* The MISC registers are not interrupt numbers */
49 { PIRQ_MISC, 0xfa, 0x00 },
50 { PIRQ_MISC0, 0x91, 0x00 },
51 { PIRQ_HPET_L, 0x00, 0x00 },
52 { PIRQ_HPET_H, 0x00, 0x00 },
Jon Murphya8590572023-02-23 13:42:52 -070053};
54
55const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
56{
57 *length = ARRAY_SIZE(fch_irq_map);
58 return fch_irq_map;
59}
60
Jon Murphy8d23d462023-02-23 13:47:44 -070061static void mainboard_configure_gpios(void)
62{
63 size_t base_num_gpios, override_num_gpios;
64 const struct soc_amd_gpio *base_gpios, *override_gpios;
65
66 baseboard_gpio_table(&base_gpios, &base_num_gpios);
67 variant_override_gpio_table(&override_gpios, &override_num_gpios);
68
69 gpio_configure_pads_with_override(base_gpios, base_num_gpios,
70 override_gpios, override_num_gpios);
71}
72
Jon Murphya8590572023-02-23 13:42:52 -070073static void mainboard_init(void *chip_info)
74{
Jon Murphy8d23d462023-02-23 13:47:44 -070075 mainboard_configure_gpios();
Jon Murphya4564582023-03-29 15:38:19 -060076 mainboard_ec_init();
Jon Murphya8590572023-02-23 13:42:52 -070077}
78
79static void mainboard_enable(struct device *dev)
80{
Jon Murphy9a2d0e62023-03-29 17:00:01 -060081 /* TODO: b/184678786 - Move into espi_config */
82 /* Unmask eSPI IRQ 1 (Keyboard) */
83 pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
Jon Murphya8590572023-02-23 13:42:52 -070084}
85
Jon Murphy2c4a4d22023-04-06 17:19:14 -060086void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
87{
88 soc_xhci_store_resources(slots, size);
89}
90
Jon Murphya8590572023-02-23 13:42:52 -070091struct chip_operations mainboard_ops = {
92 .init = mainboard_init,
93 .enable_dev = mainboard_enable,
94};