Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Felix Held | 0079200 | 2024-01-26 14:41:14 +0100 | [diff] [blame^] | 5 | #include <amdblocks/acpi.h> |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 6 | #include <amdblocks/amd_pci_util.h> |
| 7 | #include <FspsUpd.h> |
Aamir Bohra | 9fe70ed | 2021-03-31 17:35:20 +0530 | [diff] [blame] | 8 | #include <gpio.h> |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 9 | #include <soc/cpu.h> |
| 10 | #include <soc/southbridge.h> |
| 11 | #include <soc/pci_devs.h> |
Aamir Bohra | 9fe70ed | 2021-03-31 17:35:20 +0530 | [diff] [blame] | 12 | #include <soc/platform_descriptors.h> |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 13 | #include <types.h> |
| 14 | #include <commonlib/helpers.h> |
Felix Held | 2bfc6c6 | 2021-12-17 18:51:21 +0100 | [diff] [blame] | 15 | #include <soc/amd/picasso/chip.h> |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 16 | #include "gpio.h" |
Aamir Bohra | 9fe70ed | 2021-03-31 17:35:20 +0530 | [diff] [blame] | 17 | #include "mainboard.h" |
| 18 | |
| 19 | #define MAINBOARD_SHARED_DDI_PORTS 2 |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 20 | |
| 21 | /* TODO: recheck IRQ tables */ |
| 22 | |
Felix Held | cf92ecf | 2022-10-26 00:59:13 +0200 | [diff] [blame] | 23 | /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is |
| 24 | accessed via I/O ports 0xc00/0xc01. */ |
Felix Held | 067f703 | 2022-10-25 23:30:43 +0200 | [diff] [blame] | 25 | static const struct fch_irq_routing fch_irq_map[] = { |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 26 | { PIRQ_A, 8, 16 }, |
| 27 | { PIRQ_B, 10, 17 }, |
| 28 | { PIRQ_C, 11, 18 }, |
| 29 | { PIRQ_D, 12, 19 }, |
Felix Held | 8c41000 | 2023-01-14 00:39:08 +0100 | [diff] [blame] | 30 | { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 31 | { PIRQ_SD, PIRQ_NC, 16 }, |
| 32 | { PIRQ_SDIO, PIRQ_NC, 16 }, |
| 33 | { PIRQ_SATA, PIRQ_NC, 19 }, |
| 34 | { PIRQ_EMMC, PIRQ_NC, 17 }, |
| 35 | { PIRQ_GPIO, 7, 7 }, |
| 36 | { PIRQ_I2C2, 6, 6 }, |
| 37 | { PIRQ_I2C3, 14, 14 }, |
| 38 | { PIRQ_UART0, 4, 4 }, |
| 39 | { PIRQ_UART1, 3, 3 }, |
| 40 | { PIRQ_UART2, 4, 4 }, |
| 41 | { PIRQ_UART3, 3, 3 }, |
| 42 | |
| 43 | /* The MISC registers are not interrupt numbers */ |
| 44 | { PIRQ_MISC, 0xfa, 0x00 }, |
| 45 | { PIRQ_MISC0, 0x91, 0x00 }, |
| 46 | { PIRQ_MISC1, 0x00, 0x00 }, |
| 47 | { PIRQ_MISC2, 0x00, 0x00 }, |
| 48 | }; |
| 49 | |
Felix Held | cf92ecf | 2022-10-26 00:59:13 +0200 | [diff] [blame] | 50 | const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) |
Felix Held | 166932c | 2022-10-25 23:40:39 +0200 | [diff] [blame] | 51 | { |
| 52 | *length = ARRAY_SIZE(fch_irq_map); |
| 53 | return fch_irq_map; |
| 54 | } |
| 55 | |
Aamir Bohra | 9fe70ed | 2021-03-31 17:35:20 +0530 | [diff] [blame] | 56 | static void program_display_sel_gpios(void) |
| 57 | { |
| 58 | int idx, port_type; |
| 59 | gpio_t display_sel[MAINBOARD_SHARED_DDI_PORTS] = {GPIO_29, GPIO_31}; |
| 60 | |
| 61 | for (idx = 0; idx < MAINBOARD_SHARED_DDI_PORTS; idx++) { |
| 62 | port_type = get_ddi_port_conn_type(idx); |
| 63 | |
| 64 | if (port_type == HDMI) |
| 65 | gpio_output(display_sel[idx], 0); |
| 66 | else if (port_type == DP) |
| 67 | gpio_output(display_sel[idx], 1); |
| 68 | } |
| 69 | |
| 70 | } |
| 71 | |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 72 | static void mainboard_init(void *chip_info) |
| 73 | { |
| 74 | struct soc_amd_picasso_config *cfg = config_of_soc(); |
| 75 | |
| 76 | if (!CONFIG(BILBY_LPC)) |
| 77 | cfg->emmc_config.timing = SD_EMMC_EMMC_HS400; |
| 78 | |
| 79 | mainboard_program_gpios(); |
| 80 | |
Aamir Bohra | 9fe70ed | 2021-03-31 17:35:20 +0530 | [diff] [blame] | 81 | program_display_sel_gpios(); |
| 82 | |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 83 | /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */ |
| 84 | if (CONFIG(BILBY_LPC)) |
| 85 | printk(BIOS_INFO, "eMMC not available due to LPC requirement\n"); |
| 86 | else |
| 87 | mainboard_program_emmc_gpios(); |
| 88 | } |
| 89 | |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 90 | struct chip_operations mainboard_ops = { |
| 91 | .init = mainboard_init, |
Ritul Guru | 286c2f6 | 2021-02-05 23:53:28 +0530 | [diff] [blame] | 92 | }; |