Angel Pons | 560796c | 2020-04-03 01:22:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 2 | |
Kyösti Mälkki | 525930b | 2017-09-23 16:21:02 +0300 | [diff] [blame] | 3 | #include <AGESA.h> |
Krystian Hebel | f77f2c7 | 2019-04-19 17:59:38 +0200 | [diff] [blame] | 4 | #include <northbridge/amd/agesa/state_machine.h> |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 5 | |
Michał Żygowski | 8e23270 | 2021-04-29 17:53:10 +0200 | [diff] [blame] | 6 | #include "gpio_ftns.h" |
| 7 | |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 8 | static const PCIe_PORT_DESCRIPTOR PortList[] = { |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 9 | { |
| 10 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 11 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), |
| 12 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 13 | HotplugDisabled, |
| 14 | PcieGenMaxSupported, |
| 15 | PcieGenMaxSupported, |
Michał Żygowski | 8e46d42 | 2020-03-20 16:19:55 +0100 | [diff] [blame] | 16 | AspmL0sL1, |
Michał Żygowski | 869ac71 | 2020-04-04 08:49:21 +0000 | [diff] [blame] | 17 | 0x01, |
Michał Żygowski | 03a3404 | 2020-03-31 13:36:23 +0200 | [diff] [blame] | 18 | 0) |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 19 | }, |
| 20 | /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ |
| 21 | { |
| 22 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 23 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), |
| 24 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 25 | HotplugDisabled, |
| 26 | PcieGenMaxSupported, |
| 27 | PcieGenMaxSupported, |
Michał Żygowski | 8e46d42 | 2020-03-20 16:19:55 +0100 | [diff] [blame] | 28 | AspmL0sL1, |
Michał Żygowski | 869ac71 | 2020-04-04 08:49:21 +0000 | [diff] [blame] | 29 | 0x02, |
Michał Żygowski | 03a3404 | 2020-03-31 13:36:23 +0200 | [diff] [blame] | 30 | 0) |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 31 | }, |
| 32 | /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ |
| 33 | { |
| 34 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 35 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), |
| 36 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 37 | HotplugDisabled, |
| 38 | PcieGenMaxSupported, |
| 39 | PcieGenMaxSupported, |
Michał Żygowski | 8e46d42 | 2020-03-20 16:19:55 +0100 | [diff] [blame] | 40 | AspmL0sL1, |
Michał Żygowski | 869ac71 | 2020-04-04 08:49:21 +0000 | [diff] [blame] | 41 | 0x03, |
Michał Żygowski | 03a3404 | 2020-03-31 13:36:23 +0200 | [diff] [blame] | 42 | 0) |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 43 | }, |
| 44 | /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ |
| 45 | { |
| 46 | 0, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 47 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), |
| 48 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 49 | HotplugDisabled, |
| 50 | PcieGenMaxSupported, |
| 51 | PcieGenMaxSupported, |
Michał Żygowski | 8e46d42 | 2020-03-20 16:19:55 +0100 | [diff] [blame] | 52 | AspmL0sL1, |
Michał Żygowski | 869ac71 | 2020-04-04 08:49:21 +0000 | [diff] [blame] | 53 | 0x04, |
Michał Żygowski | 03a3404 | 2020-03-31 13:36:23 +0200 | [diff] [blame] | 54 | 0) |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 55 | }, |
| 56 | /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ |
| 57 | { |
| 58 | DESCRIPTOR_TERMINATE_LIST, |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 59 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), |
| 60 | PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 61 | HotplugDisabled, |
| 62 | PcieGenMaxSupported, |
| 63 | PcieGenMaxSupported, |
Michał Żygowski | 8e46d42 | 2020-03-20 16:19:55 +0100 | [diff] [blame] | 64 | AspmL0sL1, |
Michał Żygowski | 869ac71 | 2020-04-04 08:49:21 +0000 | [diff] [blame] | 65 | 0x05, |
Michał Żygowski | 03a3404 | 2020-03-31 13:36:23 +0200 | [diff] [blame] | 66 | 0) |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 67 | } |
| 68 | }; |
| 69 | |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 70 | static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { |
| 71 | .Flags = DESCRIPTOR_TERMINATE_LIST, |
| 72 | .SocketId = 0, |
| 73 | .PciePortList = PortList, |
Kyösti Mälkki | 7747757 | 2017-01-14 13:01:16 +0200 | [diff] [blame] | 74 | .DdiLinkList = NULL, |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 75 | }; |
| 76 | |
Krystian Hebel | f77f2c7 | 2019-04-19 17:59:38 +0200 | [diff] [blame] | 77 | void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 78 | { |
| 79 | InitEarly->GnbConfig.PcieComplexList = &PcieComplex; |
Michał Żygowski | 7bfdf5b | 2019-02-04 15:22:01 +0100 | [diff] [blame] | 80 | InitEarly->PlatformConfig.CStateMode = CStateModeC6; |
| 81 | InitEarly->PlatformConfig.CpbMode = CpbModeAuto; |
Piotr Król | dcd2f17 | 2016-05-27 12:04:13 +0200 | [diff] [blame] | 82 | } |
Michał Żygowski | 8e23270 | 2021-04-29 17:53:10 +0200 | [diff] [blame] | 83 | |
| 84 | void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) |
| 85 | { |
| 86 | /* |
| 87 | * Bank interleaving does not work on this platform. |
| 88 | * Disable it so AGESA will return success. |
| 89 | */ |
| 90 | Post->MemConfig.EnableBankIntlv = FALSE; |
| 91 | /* 4GB variants have ECC */ |
| 92 | if (get_spd_offset()) |
| 93 | Post->MemConfig.EnableEccFeature = TRUE; |
| 94 | else |
| 95 | Post->MemConfig.EnableEccFeature = FALSE; |
| 96 | } |