soc/intel/skylake: Add option to disable host reads to PMC XRAM
FSP disables host access to shadowed PMC XRAM registers by default,
it also provides a UPD to enable/disable host reads to these regiters.
Expose the same in devicetree as a config option.
Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18319
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 445dcb6..fbd10a9 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -402,6 +402,9 @@
*/
u32 PrmrrSize;
+ /* Enable/Disable host reads to PMC XRAM registers */
+ u8 PchPmPmcReadDisable;
+
/* Statically clock gate 8254 PIT. */
u8 clock_gate_8254;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 851c957..2d9b864 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -258,6 +258,9 @@
params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt;
params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
+ /* Enable PMC XRAM read */
+ tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable;
+
soc_irq_settings(params);
}