| config SOC_INTEL_SKYLAKE |
| bool |
| help |
| Intel Skylake support |
| |
| if SOC_INTEL_SKYLAKE |
| |
| config CPU_SPECIFIC_OPTIONS |
| def_bool y |
| select ARCH_BOOTBLOCK_X86_32 |
| select ARCH_RAMSTAGE_X86_32 |
| select ARCH_ROMSTAGE_X86_32 |
| select ARCH_VERSTAGE_X86_32 |
| select ALWAYS_LOAD_OPROM |
| select BACKUP_DEFAULT_SMM_REGION |
| select CACHE_MRC_SETTINGS |
| select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
| select CACHE_ROM |
| select CAR_MIGRATION |
| select COLLECT_TIMESTAMPS |
| select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| select CPU_MICROCODE_IN_CBFS |
| select GENERIC_GPIO_LIB |
| select HAS_PRECBMEM_TIMESTAMP_REGION |
| select HAVE_HARD_RESET |
| select HAVE_MONOTONIC_TIMER |
| select HAVE_SMI_HANDLER |
| select HAVE_UART_MEMORY_MAPPED |
| select IOAPIC |
| select MMCONF_SUPPORT |
| select MMCONF_SUPPORT_DEFAULT |
| select PARALLEL_MP |
| select PCIEXP_ASPM |
| select PCIEXP_COMMON_CLOCK |
| select PCIEXP_CLK_PM |
| select PCIEXP_L1_SUB_STATE |
| select PLATFORM_USES_FSP1_1 |
| select REG_SCRIPT |
| select RELOCATABLE_MODULES |
| select RELOCATABLE_RAMSTAGE |
| select SOC_INTEL_COMMON |
| select SOC_INTEL_COMMON_FSP_RAM_INIT |
| select SOC_INTEL_COMMON_FSP_ROMSTAGE |
| select SOC_INTEL_COMMON_RESET |
| select SOC_INTEL_COMMON_STACK |
| select SOC_INTEL_COMMON_STAGE_CACHE |
| select SMM_MODULES |
| select SMM_TSEG |
| select SMP |
| select SPI_FLASH |
| select SSE2 |
| select SUPPORT_CPU_UCODE_IN_CBFS |
| select TSC_CONSTANT_RATE |
| select TSC_SYNC_MFENCE |
| select UDELAY_TSC |
| select USE_GENERIC_FSP_CAR_INC |
| |
| config BOOTBLOCK_CPU_INIT |
| string |
| default "soc/intel/skylake/bootblock/cpu.c" |
| |
| config BOOTBLOCK_NORTHBRIDGE_INIT |
| string |
| default "soc/intel/skylake/bootblock/systemagent.c" |
| |
| config BOOTBLOCK_RESETS |
| string |
| default "soc/intel/common/reset.c" |
| |
| config BOOTBLOCK_SOUTHBRIDGE_INIT |
| string |
| default "soc/intel/skylake/bootblock/pch.c" |
| |
| config CPU_ADDR_BITS |
| int |
| default 36 |
| |
| config DCACHE_RAM_BASE |
| hex "Base address of cache-as-RAM" |
| default 0xfef00000 |
| |
| config DCACHE_RAM_SIZE |
| hex "Length in bytes of cache-as-RAM" |
| default 0x4000 |
| help |
| The size of the cache-as-ram region required during bootblock |
| and/or romstage. |
| |
| config HAVE_IFD_BIN |
| bool "Use Intel Firmware Descriptor from existing binary" |
| default n |
| |
| config BUILD_WITH_FAKE_IFD |
| bool "Build with a fake IFD" |
| default y if !HAVE_IFD_BIN |
| help |
| If you don't have an Intel Firmware Descriptor (ifd.bin) for your |
| board, you can select this option and coreboot will build without it. |
| Though, the resulting coreboot.rom will not contain all parts required |
| to get coreboot running on your board. You can however write only the |
| BIOS section to your board's flash ROM and keep the other sections |
| untouched. Unfortunately the current version of flashrom doesn't |
| support this yet. But there is a patch pending [1]. |
| |
| WARNING: Never write a complete coreboot.rom to your flash ROM if it |
| was built with a fake IFD. It just won't work. |
| |
| [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html |
| |
| config HAVE_ME_BIN |
| bool "Add Intel Management Engine firmware" |
| default y |
| help |
| The Intel processor in the selected system requires a special firmware |
| for an integrated controller called Management Engine (ME). The ME |
| firmware might be provided in coreboot's 3rdparty/blobs repository. If |
| not and if you don't have the firmware elsewhere, you can still |
| build coreboot without it. In this case however, you'll have to make |
| sure that you don't overwrite your ME firmware on your flash ROM. |
| |
| config HEAP_SIZE |
| hex |
| default 0x80000 |
| |
| config IED_REGION_SIZE |
| hex |
| default 0x400000 |
| |
| config IFD_BIN_PATH |
| string "Path to intel firmware descriptor" |
| depends on !BUILD_WITH_FAKE_IFD |
| default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
| |
| config IFD_BIOS_SECTION |
| depends on BUILD_WITH_FAKE_IFD |
| string |
| default "" |
| |
| config IFD_ME_SECTION |
| depends on BUILD_WITH_FAKE_IFD |
| string |
| default "" |
| |
| config IFD_PLATFORM_SECTION |
| depends on BUILD_WITH_FAKE_IFD |
| string |
| default "" |
| |
| config ME_BIN_PATH |
| string "Path to management engine firmware" |
| depends on HAVE_ME_BIN |
| default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" |
| |
| config MMCONF_BASE_ADDRESS |
| hex "MMIO Base Address" |
| default 0xe0000000 |
| |
| config MONOTONIC_TIMER_MSR |
| def_bool y |
| select HAVE_MONOTONIC_TIMER |
| help |
| Provide a monotonic timer using the 24MHz MSR counter. |
| |
| config PRE_GRAPHICS_DELAY |
| int "Graphics initialization delay in ms" |
| default 0 |
| help |
| On some systems, coreboot boots so fast that connected monitors |
| (mostly TVs) won't be able to wake up fast enough to talk to the |
| VBIOS. On those systems we need to wait for a bit before executing |
| the VBIOS. |
| |
| config SERIAL_CPU_INIT |
| bool |
| default n |
| |
| config SERIRQ_CONTINUOUS_MODE |
| bool |
| default y |
| help |
| If you set this option to y, the serial IRQ machine will be |
| operated in continuous mode. |
| |
| config SMM_RESERVED_SIZE |
| hex |
| default 0x200000 |
| |
| config SMM_TSEG_SIZE |
| hex |
| default 0x800000 |
| |
| config VGA_BIOS_ID |
| string |
| default "8086,0406" |
| |
| config UART_DEBUG |
| bool "Enable UART debug port." |
| default y if CONSOLE_SERIAL |
| default n |
| select DRIVERS_UART |
| select DRIVERS_UART_8250MEM |
| select DRIVERS_UART_8250MEM_32 |
| |
| endif |