Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
fe481eb3e5e8e8d39d892bfcfe085bc7d49ff886
/
.
/
src
/
northbridge
/
intel
/
e7505
/
Makefile.inc
blob: 4eda3d10496232b8abbffd890768127551904f60 [
file
] [
log
] [
blame
]
ifeq
(
$
(
CONFIG_NORTHBRIDGE_INTEL_E7505
),
y
)
ramstage
-
y
+=
northbridge
.
c
ramstage
-
y
+=
memmap
.
c
romstage
-
y
+=
raminit
.
c
romstage
-
y
+=
memmap
.
c
postcar
-
y
+=
memmap
.
c
endif