soc/intel/apl: Use Kconfig to enable CseRbp
This patch makes SKIP_CSE_RBP=y default for Apollo Lake if Boot Device is
memory mapped and ensures SkipCseRbp UPD is guarded against this config.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifd01a25443e2582a90529e55be8d34a88342a103
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 38e7491..f9ad4d6 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -117,6 +117,15 @@
# provide a custom media driver that facilitates mapping
select X86_CUSTOM_BOOTMEDIA
+config SKIP_CSE_RBP
+ bool
+ default y if BOOT_DEVICE_MEMORY_MAPPED
+ help
+ Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch
+ firmware for us if we are using memory-mapped SPI. This lets CSE
+ state machine transition to next boot state, so that it can function
+ as designed.
+
config DISABLE_HECI1_AT_PRE_BOOT
default y
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index c4d7977..08543b1 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -293,14 +293,7 @@
/* Do NOT let FSP do any GPIO pad configuration */
mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL;
- /*
- * Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch
- * firmware for us if we are using memory-mapped SPI. This lets CSE
- * state machine transition to next boot state, so that it can function
- * as designed.
- */
- mupd->FspmConfig.SkipCseRbp =
- CONFIG(BOOT_DEVICE_MEMORY_MAPPED);
+ mupd->FspmConfig.SkipCseRbp = CONFIG(SKIP_CSE_RBP);
/*
* Converged Security Engine (CSE) has secure storage functionality.