Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * inteltool - dump all registers on an Intel CPU + chipset based system. |
| 3 | * |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 4 | * Copyright (C) 2008-2010 by coresystems GmbH |
| 5 | * |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <stdio.h> |
| 22 | #include <stdlib.h> |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 23 | #include <inttypes.h> |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 24 | #include "inteltool.h" |
| 25 | |
Vladimir Serbinenko | e4e8e09 | 2013-03-31 13:51:37 +0200 | [diff] [blame] | 26 | volatile uint8_t *mchbar; |
| 27 | |
| 28 | static void write_mchbar32 (uint32_t addr, uint32_t val) |
| 29 | { |
| 30 | * (volatile uint32_t *) (mchbar + addr) = val; |
| 31 | } |
| 32 | |
| 33 | static uint32_t read_mchbar32 (uint32_t addr) |
| 34 | { |
| 35 | return * (volatile uint32_t *) (mchbar + addr); |
| 36 | } |
| 37 | |
| 38 | static uint8_t read_mchbar8 (uint32_t addr) |
| 39 | { |
| 40 | return * (volatile uint8_t *) (mchbar + addr); |
| 41 | } |
| 42 | |
| 43 | static u16 read_500 (int channel, u16 addr, int split) |
| 44 | { |
| 45 | uint32_t val; |
| 46 | write_mchbar32 (0x500 + (channel << 10), 0); |
| 47 | while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000); |
| 48 | write_mchbar32 (0x500 + (channel << 10), 0x80000000 | (((read_mchbar8 (0x246 + (channel << 10)) >> 2) & 3) + 0xb88 - addr)); |
| 49 | while (read_mchbar32 (0x500 + (channel << 10)) & 0x800000); |
| 50 | val = read_mchbar32 (0x508 + (channel << 10)); |
| 51 | |
| 52 | return val & ((1 << split) - 1); |
| 53 | } |
| 54 | |
| 55 | static inline u16 get_lane_offset (int slot, int rank, int lane) |
| 56 | { |
| 57 | return 0x124 * lane + ((lane & 4) ? 0x23e : 0) + 11 * rank + 22 * slot - 0x452 * (lane == 8); |
| 58 | } |
| 59 | |
| 60 | static inline u16 get_timing_register_addr (int lane, int tm, int slot, int rank) |
| 61 | { |
| 62 | const u16 offs[] = { 0x1d, 0xa8, 0xe6, 0x5c }; |
| 63 | return get_lane_offset (slot, rank, lane) + offs[(tm + 3) % 4]; |
| 64 | } |
| 65 | |
| 66 | static void write_1d0 (u32 val, u16 addr, int bits, int flag) |
| 67 | { |
| 68 | write_mchbar32 (0x1d0, 0); |
| 69 | while (read_mchbar32 (0x1d0) & 0x800000); |
| 70 | write_mchbar32 (0x1d4, (val & ((1 << bits) - 1)) | (2 << bits) | (flag << bits)); |
| 71 | write_mchbar32 (0x1d0, 0x40000000 | addr); |
| 72 | while (read_mchbar32 (0x1d0) & 0x800000); |
| 73 | } |
| 74 | |
| 75 | static u16 read_1d0 (u16 addr, int split) |
| 76 | { |
| 77 | u32 val; |
| 78 | write_mchbar32 (0x1d0, 0); |
| 79 | while (read_mchbar32 (0x1d0) & 0x800000); |
| 80 | write_mchbar32 (0x1d0, 0x80000000 | (((read_mchbar8 (0x246) >> 2) & 3) + 0x361 - addr)); |
| 81 | while (read_mchbar32 (0x1d0) & 0x800000); |
| 82 | val = read_mchbar32 (0x1d8); |
| 83 | write_1d0 (0, 0x33d, 0, 0); |
| 84 | write_1d0 (0, 0x33d, 0, 0); |
| 85 | return val & ((1 << split) - 1); |
| 86 | } |
| 87 | |
| 88 | static void dump_timings (void) |
| 89 | { |
| 90 | int channel, slot, rank, lane, i; |
| 91 | printf ("Timings:\n"); |
| 92 | for (channel = 0; channel < 2; channel++) |
| 93 | for (slot = 0; slot < 2; slot++) |
| 94 | for (rank = 0; rank < 2; rank++) { |
| 95 | printf ("channel %d, slot %d, rank %d\n", channel, slot, rank); |
| 96 | for (lane = 0; lane < 9; lane++) { |
| 97 | printf ("lane %d: ", lane); |
| 98 | for (i = 0; i < 4; i++) { |
| 99 | printf ("%x ", read_500 (channel, |
| 100 | get_timing_register_addr (lane, i, slot, rank), 9)); |
| 101 | } |
| 102 | printf ("\n"); |
| 103 | } |
| 104 | } |
| 105 | |
| 106 | printf ("[178] = %x\n", read_1d0 (0x178, 7)); |
| 107 | printf ("[10b] = %x\n", read_1d0 (0x10b, 6)); |
| 108 | } |
| 109 | |
| 110 | |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 111 | /* |
| 112 | * (G)MCH MMIO Config Space |
| 113 | */ |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 114 | int print_mchbar(struct pci_dev *nb, struct pci_access *pacc) |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 115 | { |
| 116 | int i, size = (16 * 1024); |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 117 | uint64_t mchbar_phys; |
| 118 | struct pci_dev *nb_device6; /* "overflow device" on i865 */ |
| 119 | uint16_t pcicmd6; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 120 | |
| 121 | printf("\n============= MCHBAR ============\n\n"); |
| 122 | |
| 123 | switch (nb->device_id) { |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 124 | case PCI_DEVICE_ID_INTEL_82865: |
| 125 | /* |
| 126 | * On i865, the memory access enable/disable bit (MCHBAREN on |
| 127 | * i945/i965) is not in the MCHBAR (i945/i965) register but in |
| 128 | * the PCICMD6 register. BAR6 and PCICMD6 reside on device 6. |
| 129 | * |
| 130 | * The actual base address is in BAR6 on i865 where on |
| 131 | * i945/i965 the base address is in MCHBAR. |
| 132 | */ |
| 133 | nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0); /* Device 6 */ |
| 134 | mchbar_phys = pci_read_long(nb_device6, 0x10); /* BAR6 */ |
| 135 | pcicmd6 = pci_read_long(nb_device6, 0x04); /* PCICMD6 */ |
| 136 | |
| 137 | /* Try to enable Memory Access Enable (MAE). */ |
| 138 | if (!(pcicmd6 & (1 << 1))) { |
| 139 | printf("Access to BAR6 is currently disabled, " |
| 140 | "attempting to enable.\n"); |
| 141 | pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1)); |
| 142 | if (pci_read_long(nb_device6, 0x04) & (1 << 1)) |
| 143 | printf("Enabled successfully.\n"); |
| 144 | else |
| 145 | printf("Enable FAILED!\n"); |
| 146 | } |
| 147 | mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */ |
| 148 | break; |
Pat Erley | ca3548e | 2010-04-21 06:23:19 +0000 | [diff] [blame] | 149 | case PCI_DEVICE_ID_INTEL_82915: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 150 | case PCI_DEVICE_ID_INTEL_82945GM: |
Björn Busse | 2d33dc4 | 2010-08-01 15:33:30 +0000 | [diff] [blame] | 151 | case PCI_DEVICE_ID_INTEL_82945GSE: |
Stefan Reinauer | 3d9a12f | 2008-11-02 11:11:40 +0000 | [diff] [blame] | 152 | case PCI_DEVICE_ID_INTEL_82945P: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 153 | case PCI_DEVICE_ID_INTEL_82975X: |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 154 | mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe; |
| 155 | break; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 156 | case PCI_DEVICE_ID_INTEL_82965PM: |
| 157 | case PCI_DEVICE_ID_INTEL_82Q35: |
| 158 | case PCI_DEVICE_ID_INTEL_82G33: |
| 159 | case PCI_DEVICE_ID_INTEL_82Q33: |
| 160 | mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; |
| 161 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 162 | break; |
Stefan Tauner | 1a00cf0 | 2012-10-13 06:23:52 +0200 | [diff] [blame] | 163 | case PCI_DEVICE_ID_INTEL_82946: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 164 | case PCI_DEVICE_ID_INTEL_82Q965: |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 165 | case PCI_DEVICE_ID_INTEL_ATOM_DXXX: |
| 166 | case PCI_DEVICE_ID_INTEL_ATOM_NXXX: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 167 | mchbar_phys = pci_read_long(nb, 0x48); |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 168 | |
| 169 | /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads. |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 170 | * If it isn't, try to set it. This may fail, because there is |
| 171 | * some bit that locks that bit, and isn't in the public |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 172 | * datasheets. |
| 173 | */ |
| 174 | |
| 175 | if(!(mchbar_phys & 1)) |
| 176 | { |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 177 | printf("Access to the MCHBAR is currently disabled, " |
| 178 | "attempting to enable.\n"); |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 179 | mchbar_phys |= 0x1; |
| 180 | pci_write_long(nb, 0x48, mchbar_phys); |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 181 | if(pci_read_long(nb, 0x48) & 1) |
Corey Osgood | 23d98c7 | 2010-07-29 19:25:31 +0000 | [diff] [blame] | 182 | printf("Enabled successfully.\n"); |
| 183 | else |
| 184 | printf("Enable FAILED!\n"); |
| 185 | } |
| 186 | mchbar_phys &= 0xfffffffe; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 187 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 188 | break; |
Maciej Pijanka | 90d1740 | 2009-09-30 17:05:46 +0000 | [diff] [blame] | 189 | case PCI_DEVICE_ID_INTEL_82443LX: |
| 190 | case PCI_DEVICE_ID_INTEL_82443BX: |
Stefan Reinauer | b2aedb1 | 2009-08-29 15:45:43 +0000 | [diff] [blame] | 191 | case PCI_DEVICE_ID_INTEL_82810: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 192 | case PCI_DEVICE_ID_INTEL_82810E_DC: |
| 193 | case PCI_DEVICE_ID_INTEL_82810_DC: |
Stefan Reinauer | 0484481 | 2010-02-22 11:26:06 +0000 | [diff] [blame] | 194 | case PCI_DEVICE_ID_INTEL_82830M: |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 195 | printf("This northbridge does not have MCHBAR.\n"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 196 | return 1; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 197 | case PCI_DEVICE_ID_INTEL_82X4X: |
| 198 | case PCI_DEVICE_ID_INTEL_82X38: |
Ruud Schramp | bb41f50 | 2011-04-04 07:53:19 +0200 | [diff] [blame] | 199 | case PCI_DEVICE_ID_INTEL_32X0: |
Anton Kochkov | da0b456 | 2010-05-30 12:33:12 +0000 | [diff] [blame] | 200 | mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe; |
| 201 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 202 | break; |
| 203 | case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: |
| 204 | mchbar_phys = pci_read_long(nb, 0x48); |
| 205 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 206 | mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */ |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 207 | break; |
Felix Held | 0cc8f29 | 2014-11-05 03:18:44 +0100 | [diff] [blame] | 208 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 209 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
Damien Zammit | 601da48 | 2014-05-26 23:00:23 +1000 | [diff] [blame] | 210 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: /* pretty printing not implemented yet */ |
| 211 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B: |
| 212 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C: |
| 213 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: |
Dennis Wassenberg | ae6685f | 2014-10-30 10:30:40 +0100 | [diff] [blame] | 214 | case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: |
Stefan Tauner | 04c0600 | 2012-10-13 02:19:30 +0200 | [diff] [blame] | 215 | mchbar_phys = pci_read_long(nb, 0x48); |
| 216 | mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; |
| 217 | mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ |
Vladimir Serbinenko | 44bc11c | 2014-08-16 19:14:02 +0200 | [diff] [blame] | 218 | size = 32768; |
Anton Kochkov | c7fc442 | 2012-07-21 06:36:47 +0400 | [diff] [blame] | 219 | break; |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 220 | default: |
| 221 | printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); |
| 222 | return 1; |
| 223 | } |
| 224 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 225 | mchbar = map_physical(mchbar_phys, size); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 226 | |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 227 | if (mchbar == NULL) { |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 228 | if (nb->device_id == PCI_DEVICE_ID_INTEL_82865) |
| 229 | perror("Error mapping BAR6"); |
| 230 | else |
| 231 | perror("Error mapping MCHBAR"); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 232 | exit(1); |
| 233 | } |
| 234 | |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 235 | if (nb->device_id == PCI_DEVICE_ID_INTEL_82865) |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 236 | printf("BAR6 = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); |
Idwer Vollering | 312fc96 | 2010-12-17 22:34:58 +0000 | [diff] [blame] | 237 | else |
Stefan Reinauer | a7b296d | 2011-11-14 12:40:34 -0800 | [diff] [blame] | 238 | printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 239 | |
Vladimir Serbinenko | 9c4f1b8 | 2014-11-04 21:05:12 +0100 | [diff] [blame] | 240 | for (i = 0; i < size; i += 4) { |
| 241 | if (*(uint32_t *)(mchbar + i)) |
| 242 | printf("0x%04x: 0x%08"PRIx32"\n", i, *(uint32_t *)(mchbar+i)); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 243 | } |
| 244 | |
Vladimir Serbinenko | 44bc11c | 2014-08-16 19:14:02 +0200 | [diff] [blame] | 245 | switch (nb->device_id) |
| 246 | { |
| 247 | case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN: |
Vladimir Serbinenko | e4e8e09 | 2013-03-31 13:51:37 +0200 | [diff] [blame] | 248 | printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1); |
| 249 | dump_timings (); |
Vladimir Serbinenko | 44bc11c | 2014-08-16 19:14:02 +0200 | [diff] [blame] | 250 | break; |
| 251 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_A: |
| 252 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_B: |
| 253 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_C: |
| 254 | case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D: |
Felix Held | 0cc8f29 | 2014-11-05 03:18:44 +0100 | [diff] [blame] | 255 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D: |
| 256 | case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M: |
Vladimir Serbinenko | 44bc11c | 2014-08-16 19:14:02 +0200 | [diff] [blame] | 257 | ivybridge_dump_timings(); |
| 258 | break; |
Vladimir Serbinenko | e4e8e09 | 2013-03-31 13:51:37 +0200 | [diff] [blame] | 259 | } |
Stefan Reinauer | 1162f25 | 2008-12-04 15:18:20 +0000 | [diff] [blame] | 260 | unmap_physical((void *)mchbar, size); |
Stefan Reinauer | 2319027 | 2008-08-20 13:41:24 +0000 | [diff] [blame] | 261 | return 0; |
| 262 | } |
| 263 | |
| 264 | |