riscv: Use correct argument in a1 when invoking payload
Fix a bug introduced by:
820dcfceb3901dbb00bb90c876e374126ca14e20
riscv: Simplify payload handling
Put fdt into a1 correctly.
Change-Id: I0dea7b88fde9d9a7365cb366917747d8110b9159
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31287
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
index 8a07ff8..f3ed5a4 100644
--- a/src/arch/riscv/payload.c
+++ b/src/arch/riscv/payload.c
@@ -44,7 +44,7 @@
write_csr(mepc, doit);
asm volatile(
"mv a0, %0\n\t"
- "mv a1, %0\n\t"
+ "mv a1, %1\n\t"
"mret" ::"r"(hart_id),
"r"(fdt)
: "a0", "a1");