lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check
Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM
on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also
uses bit 29 for root port #6. Correct the bit used in the check, as well
as the surrounding comments.
Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c
index ef03eee..966a25d 100644
--- a/src/soc/intel/broadwell/pch/pcie.c
+++ b/src/soc/intel/broadwell/pch/pcie.c
@@ -452,17 +452,17 @@
break;
case 5:
/*
- * Bit 28 of b0d28f4 0x32c register correspond to
- * Root Ports 4:1.
+ * Bit 28 of b0d28f4 0x32c register corresponds to
+ * Root Port 5.
*/
do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
break;
case 6:
/*
- * Bit 28 of b0d28f5 0x32c register correspond to
- * Root Ports 4:1.
+ * Bit 29 of b0d28f5 0x32c register corresponds to
+ * Root Port 6.
*/
- do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
+ do_aspm = !!(rpc.b0d28f5_32c & (1 << 29));
break;
}
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 7f5e1fa..0c17c9c 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -518,17 +518,17 @@
break;
case 5:
/*
- * Bit 28 of b0d28f4 0x32c register correspond to
- * Root Ports 4:1.
+ * Bit 28 of b0d28f4 0x32c register corresponds to
+ * Root Port 5.
*/
do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
break;
case 6:
/*
- * Bit 28 of b0d28f5 0x32c register correspond to
- * Root Ports 4:1.
+ * Bit 29 of b0d28f5 0x32c register corresponds to
+ * Root Port 6.
*/
- do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
+ do_aspm = !!(rpc.b0d28f5_32c & (1 << 29));
break;
}
} else {