diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c
index ef03eee..966a25d 100644
--- a/src/soc/intel/broadwell/pch/pcie.c
+++ b/src/soc/intel/broadwell/pch/pcie.c
@@ -452,17 +452,17 @@
 		break;
 	case 5:
 		/*
-		 * Bit 28 of b0d28f4 0x32c register correspond to
-		 * Root Ports 4:1.
+		 * Bit 28 of b0d28f4 0x32c register corresponds to
+		 * Root Port 5.
 		 */
 		do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
 		break;
 	case 6:
 		/*
-		 * Bit 28 of b0d28f5 0x32c register correspond to
-		 * Root Ports 4:1.
+		 * Bit 29 of b0d28f5 0x32c register corresponds to
+		 * Root Port 6.
 		 */
-		do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
+		do_aspm = !!(rpc.b0d28f5_32c & (1 << 29));
 		break;
 	}
 
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 7f5e1fa..0c17c9c 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -518,17 +518,17 @@
 			break;
 		case 5:
 			/*
-			 * Bit 28 of b0d28f4 0x32c register correspond to
-			 * Root Ports 4:1.
+			 * Bit 28 of b0d28f4 0x32c register corresponds to
+			 * Root Port 5.
 			 */
 			do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
 			break;
 		case 6:
 			/*
-			 * Bit 28 of b0d28f5 0x32c register correspond to
-			 * Root Ports 4:1.
+			 * Bit 29 of b0d28f5 0x32c register corresponds to
+			 * Root Port 6.
 			 */
-			do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
+			do_aspm = !!(rpc.b0d28f5_32c & (1 << 29));
 			break;
 		}
 	} else {