| /* SPDX-License-Identifier: GPL-2.0-only */ |
| /* This file is part of the coreboot project. */ |
| |
| /* Note: Only need HID on Primary Bus */ |
| External (TOM1) |
| External (TOM2) |
| Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ |
| Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ |
| |
| /* Describe the Northbridge devices */ |
| |
| Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ |
| { |
| Return(Zero) |
| } |
| |
| Method(_STA, 0, NotSerialized) |
| { |
| Return(0x0B) /* Status is visible */ |
| } |
| |
| Method(_PRT,0, NotSerialized) |
| { |
| If(PMOD) |
| { |
| Return(APR0) /* APIC mode */ |
| } |
| Return (PR0) /* PIC Mode */ |
| } |
| |
| Device(AMRT) { |
| Name(_ADR, 0x00000000) |
| } /* end AMRT */ |
| |
| /* Gpp 0 */ |
| Device(PBR4) { |
| Name(_ADR, 0x00020001) |
| Method(_PRT,0) { |
| If(PMOD){ Return(APS4) } /* APIC mode */ |
| Return (PS4) /* PIC Mode */ |
| } /* end _PRT */ |
| } /* end PBR4 */ |
| |
| /* Gpp 1 */ |
| Device(PBR5) { |
| Name(_ADR, 0x00020002) |
| Method(_PRT,0) { |
| If(PMOD){ Return(APS5) } /* APIC mode */ |
| Return (PS5) /* PIC Mode */ |
| } /* end _PRT */ |
| } /* end PBR5 */ |
| |
| /* Gpp 2 */ |
| Device(PBR6) { |
| Name(_ADR, 0x00020003) |
| Method(_PRT,0) { |
| If(PMOD){ Return(APS6) } /* APIC mode */ |
| Return (PS6) /* PIC Mode */ |
| } /* end _PRT */ |
| } /* end PBR6 */ |
| |
| /* Gpp 3 */ |
| Device(PBR7) { |
| Name(_ADR, 0x00020004) |
| Method(_PRT,0) { |
| If(PMOD){ Return(APS7) } /* APIC mode */ |
| Return (PS7) /* PIC Mode */ |
| } /* end _PRT */ |
| } /* end PBR7 */ |
| |
| /* Gpp 4 */ |
| Device(PBR8) { |
| Name(_ADR, 0x00020005) |
| Method(_PRT,0) { |
| If(PMOD){ Return(APS8) } /* APIC mode */ |
| Return (PS8) /* PIC Mode */ |
| } /* end _PRT */ |
| } /* end PBR8 */ |
| |
| Device(AZHD) { /* 0:9.2 - HD Audio */ |
| Name(_ADR, 0x00090002) |
| } /* end AZHD */ |