southbridge/broadcom: Remove spaces before/after parenthesis
Change-Id: Ic43b5ddaa395658ab7c34cdd004516884a20b005
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index d9a1268..60f7da0 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -29,14 +29,14 @@
/* See if we are on the behind the pcix bridge */
bus_dev = dev->bus->dev;
if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
- (bus_dev->device == 0x0036 )) // device under PCI-X Bridge
+ (bus_dev->device == 0x0036)) // device under PCI-X Bridge
{
unsigned devfn;
devfn = bus_dev->path.pci.devfn + (1 << 3);
sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
- (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
+ (bus_dev->device == 0x0104)) // device under PCI Bridge (under PCI-X)
{
unsigned devfn;
devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
@@ -46,7 +46,7 @@
else { // same bus
unsigned devfn;
devfn = (dev->path.pci.devfn) & ~7;
- if ( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
+ if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS) {
if (dev->device == 0x0036) //PCI-X Bridge
{ devfn += (1<<3); }
else if (dev->device == 0x0223) // USB
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 02331d9..57df3d2 100644
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
@@ -42,13 +42,13 @@
write32(mmio_base + 0x10f0, 0x40000001);
write32(mmio_base + 0x8c, 0x00ff2007);
- mdelay( 10 );
+ mdelay(10);
write32(mmio_base + 0x8c, 0x78592009);
- mdelay( 10 );
+ mdelay(10);
write32(mmio_base + 0x8c, 0x00082004);
- mdelay( 10 );
+ mdelay(10);
write32(mmio_base + 0x8c, 0x00002004);
- mdelay( 10 );
+ mdelay(10);
//init PHY
diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
index ab0cd05..c129434 100644
--- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
@@ -43,9 +43,9 @@
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {
- byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
+ byte |= (1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
- if ( byte != byte_old) {
+ if (byte != byte_old) {
outb(byte, 0x70);
}
diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h
index 8ebe203..1c3c9d7 100644
--- a/src/southbridge/broadcom/bcm5785/smbus.h
+++ b/src/southbridge/broadcom/bcm5785/smbus.h
@@ -66,10 +66,10 @@
val = inb(smbus_io_base + SMBHSTSTAT);
val &= 0x1f; // mask off reserved bits
- if ( val & 0x1c) {
+ if (val & 0x1c) {
return -5; // error
}
- if ( val == 0x02) {
+ if (val == 0x02) {
outb(val, smbus_io_base + SMBHSTSTAT); // clear status
return 0; //
}