commonlib,console,nb,sb,security: Add SPDX licenses to Makefiles

To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.

Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.

This patch adds the GPL V2 license identifier to the top of all
makefiles in the commonlib, console, northbridge, security, and
southbridge directories that don't already have an SPDX license line
at the top.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I02804a10d0b0355e41271a035613d9f3dfb122f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
index e90ed4f..86e8c56 100644
--- a/src/commonlib/Makefile.inc
+++ b/src/commonlib/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 subdirs-y += storage
 
 bootblock-y += mem_pool.c
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 4296426..fd98cf7 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ramstage-y += vtxprintf.c printk.c vsprintf.c
 ramstage-y += init.c console.c
 ramstage-y += post.c
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
index fc472ea..eb2e629 100644
--- a/src/device/dram/Makefile.inc
+++ b/src/device/dram/Makefile.inc
@@ -1,3 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
 
 romstage-y += ddr_common.c
 ramstage-y += ddr_common.c spd.c
diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc
index 29ac437..44a056b 100644
--- a/src/northbridge/intel/e7505/Makefile.inc
+++ b/src/northbridge/intel/e7505/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y)
 
 ramstage-y += northbridge.c
diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc
index 72b87db..b7922d4 100644
--- a/src/security/Makefile.inc
+++ b/src/security/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 subdirs-y += vboot
 subdirs-y += tpm
 subdirs-y += memory
diff --git a/src/security/intel/Makefile.inc b/src/security/intel/Makefile.inc
index 20aea27..25e28ed 100644
--- a/src/security/intel/Makefile.inc
+++ b/src/security/intel/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 subdirs-y += txt
 subdirs-y += stm
 subdirs-y += cbnt
diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc
index 4c585b8..e166634 100644
--- a/src/security/intel/cbnt/Makefile.inc
+++ b/src/security/intel/cbnt/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y)
 
 all-y += logging.c
diff --git a/src/security/intel/stm/Makefile.inc b/src/security/intel/stm/Makefile.inc
index d4da605..90b7c18 100644
--- a/src/security/intel/stm/Makefile.inc
+++ b/src/security/intel/stm/Makefile.inc
@@ -1,3 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
 
 # put the stm where it can be found
 
diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc
index e19bacf..c1fc0c4 100644
--- a/src/security/intel/txt/Makefile.inc
+++ b/src/security/intel/txt/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 romstage-$(CONFIG_INTEL_TXT_LIB) += txtlib.c
 
 ifeq ($(CONFIG_INTEL_TXT),y)
diff --git a/src/security/memory/Makefile.inc b/src/security/memory/Makefile.inc
index 0882ca3..4f07bbb 100644
--- a/src/security/memory/Makefile.inc
+++ b/src/security/memory/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 romstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
 postcar-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
 ramstage-$(CONFIG_PLATFORM_HAS_DRAM_CLEAR) += memory.c
diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc
index ae06cb0..ade9656 100644
--- a/src/security/tpm/Makefile.inc
+++ b/src/security/tpm/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 subdirs-$(CONFIG_TPM_GOOGLE) += tss/vendor/cr50
 
 ## TSS
diff --git a/src/security/tpm/tss/vendor/cr50/Makefile.inc b/src/security/tpm/tss/vendor/cr50/Makefile.inc
index 8bacafd..0a16fa1 100644
--- a/src/security/tpm/tss/vendor/cr50/Makefile.inc
+++ b/src/security/tpm/tss/vendor/cr50/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ramstage-y += cr50.c
 romstage-y += cr50.c
 postcar-y += cr50.c
diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc
index e086dc3..ce8b3d4 100644
--- a/src/southbridge/amd/common/Makefile.inc
+++ b/src/southbridge/amd/common/Makefile.inc
@@ -1 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c
diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc
index d6ae171..83ebca5 100644
--- a/src/southbridge/intel/i82870/Makefile.inc
+++ b/src/southbridge/intel/i82870/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y)
 
 ramstage-y += ioapic.c
diff --git a/src/southbridge/ricoh/rl5c476/Makefile.inc b/src/southbridge/ricoh/rl5c476/Makefile.inc
index 3fa232f..24e84d2 100644
--- a/src/southbridge/ricoh/rl5c476/Makefile.inc
+++ b/src/southbridge/ricoh/rl5c476/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_SOUTHBRIDGE_RICOH_RL5C476),y)
 
 ramstage-y += rl5c476.c
diff --git a/src/southbridge/ti/pci1x2x/Makefile.inc b/src/southbridge/ti/pci1x2x/Makefile.inc
index 4f2a3d3..05e57ad 100644
--- a/src/southbridge/ti/pci1x2x/Makefile.inc
+++ b/src/southbridge/ti/pci1x2x/Makefile.inc
@@ -1,3 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
 ifeq ($(CONFIG_SOUTHBRIDGE_TI_PCI1X2X),y)
 
 ramstage-y += pci1x2x.c