| <!DOCTYPE html> |
| <html> |
| <head> |
| <title>FSP 1.1</title> |
| </head> |
| <body> |
| |
| <h1>x86 FSP 1.1 Integration</h1> |
| <p> |
| Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC) |
| and board support. The combined steps are listed |
| <a target="_blank" href="development.html">here</a>. |
| The development steps for FSP are listed below: |
| </p> |
| <ol> |
| <li><a href="#RequiredFiles">Required Files</a></li> |
| <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li> |
| <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li> |
| </ol> |
| |
| <p> |
| FSP Documentation: |
| </p> |
| <ul> |
| <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li> |
| </ul> |
| |
| <hr> |
| <h1><a name="RequiredFiles">Required Files</a></h1> |
| <h2><a name="corebootRequiredFiles">coreboot Required Files</a></h2> |
| <ol> |
| <li>Create the following directories if they do not already exist: |
| <ul> |
| <li>src/vendorcode/intel/fsp/fsp1_1/<Chip Family></li> |
| <li>3rdparty/blobs/mainboard/<Board Vendor>/<Board Name></li> |
| </ul> |
| </li> |
| <li> |
| The following files may need to be copied from the FSP build or release into the |
| directories above if they are not present or are out of date: |
| <ul> |
| <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h</li> |
| <li>FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin</li> |
| </ul> |
| </li> |
| </ol> |
| |
| |
| <hr> |
| <h1><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h1> |
| <p> |
| Add the FSP binary to the coreboot flash image using the following command: |
| </p> |
| <pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre> |
| <p> |
| This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the |
| FSP code for TempRamInit may be executed in place. |
| </p> |
| |
| |
| <hr> |
| <h1><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h1> |
| <p> |
| Set the following Kconfig values: |
| </p> |
| <ul> |
| <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li> |
| <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li> |
| <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li> |
| <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li> |
| </ul> |
| |
| |
| <hr> |
| <p>Modified: 17 May 2016</p> |
| </body> |
| </html> |