CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.
TODO: Check TSEG alignment, it used for MTRR programming.
Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c
index 3513c0f..9626745 100644
--- a/src/northbridge/intel/fsp_rangeley/raminit.c
+++ b/src/northbridge/intel/fsp_rangeley/raminit.c
@@ -26,19 +26,23 @@
#include "northbridge.h"
#include <drivers/intel/fsp/fsp_util.h>
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
/*
* Calculate the top of usable (low) DRAM.
* The FSP's reserved memory sits just below the SMM region,
* allowing calculation of the top of usable memory.
*/
- u32 tom = sideband_read(B_UNIT, BMBOUND);
- u32 bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
+ uintptr_t tom = sideband_read(B_UNIT, BMBOUND);
+ uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20;
if (bsmmrrl) {
tom = bsmmrrl;
}
- tom -= FSP_RESERVE_MEMORY_SIZE;
- return (unsigned long) tom;
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
}
diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
index 080a7f4..ca6f345 100644
--- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc
+++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
@@ -20,11 +20,13 @@
subdirs-y += fsp
ramstage-y += northbridge.c
+ramstage-y += ram_calc.c
ramstage-y += gma.c
ramstage-y += acpi.c
romstage-y += raminit.c
+romstage-y += ram_calc.c
romstage-y += early_init.c
romstage-y += report_platform.c
romstage-y += ../../../arch/x86/lib/walkcbfs.S
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c
index adc69bc..fac635d 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c
@@ -245,16 +245,6 @@
assign_resources(dev->link_list);
}
-unsigned long get_top_of_ram(void)
-{
- struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-
- /* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0);
- tom -= 0x200000; /* 2MB for FSP HOB */
- return (unsigned long) tom;
-}
-
/* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
diff --git a/src/northbridge/intel/fsp_sandybridge/ram_calc.c b/src/northbridge/intel/fsp_sandybridge/ram_calc.c
new file mode 100644
index 0000000..43a1105
--- /dev/null
+++ b/src/northbridge/intel/fsp_sandybridge/ram_calc.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <fsp_util.h>
+#include "northbridge.h"
+
+static uintptr_t smm_region_start(void)
+{
+ /* Base of TSEG is top of usable DRAM */
+ uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0);
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
+}
diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c
index 19b48ca..8689274 100644
--- a/src/northbridge/intel/fsp_sandybridge/raminit.c
+++ b/src/northbridge/intel/fsp_sandybridge/raminit.c
@@ -74,11 +74,3 @@
((ch_conf >> 16) & 1) ? ", selected" : "");
}
}
-
-unsigned long get_top_of_ram(void)
-{
- /* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0);
- tom -= 0x200000; /* 2MB for FSP HOB */
- return (unsigned long) tom;
-}
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index c8c15d3..d9d3357 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -86,7 +86,7 @@
}
}
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
const pci_devfn_t dev = PCI_DEV(0, 0, 0);
@@ -105,3 +105,8 @@
}
return tor;
}
+
+void *cbmem_top(void)
+{
+ return (void *) smm_region_start();
+}
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
index 99e7d67..01ad50d 100644
--- a/src/northbridge/intel/haswell/ram_calc.c
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -24,12 +24,17 @@
#include <cbmem.h>
#include "haswell.h"
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
/*
* Base of TSEG is top of usable DRAM below 4GiB. The register has
* 1 MiB alignement.
*/
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
- return (unsigned long) tom & ~((1 << 20) - 1);
+ uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+ return tom & ~((1 << 20) - 1);
+}
+
+void *cbmem_top(void)
+{
+ return (void *)smm_region_start();
}
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index d09b2e1..4b7d895 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -24,9 +24,9 @@
#include <cbmem.h>
#include "i945.h"
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
- u32 tom;
+ uintptr_t tom;
if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
/* IGD enabled, get top of Memory from BSM register */
@@ -53,5 +53,10 @@
/* TSEG either disabled or invalid */
break;
}
- return (unsigned long) tom;
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) smm_region_start();
}
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index db57a3d..d36684e 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -23,9 +23,14 @@
#include <cbmem.h>
#include "nehalem.h"
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
/* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
- return (unsigned long) tom;
+ uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) smm_region_start();
}
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index 3693a07..e147909 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -23,9 +23,14 @@
#include <cbmem.h>
#include "sandybridge.h"
-unsigned long get_top_of_ram(void)
+static uintptr_t smm_region_start(void)
{
/* Base of TSEG is top of usable DRAM */
- u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
- return (unsigned long) tom;
+ uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+ return tom;
+}
+
+void *cbmem_top(void)
+{
+ return (void *) smm_region_start();
}