Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2012 Samsung Electronics |
| 5 | * |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 18 | */ |
| 19 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 20 | /* Clock setup for SMDK5250 board based on EXYNOS5 */ |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 21 | |
| 22 | #include <console/console.h> |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 23 | #include <delay.h> |
| 24 | #include "clk.h" |
| 25 | #include "cpu.h" |
| 26 | #include "dp.h" |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 27 | #include "setup.h" |
| 28 | |
David Hendricks | 0d4f97e | 2013-02-03 18:09:58 -0800 | [diff] [blame] | 29 | void system_clock_init(struct mem_timings *mem, |
| 30 | struct arm_clk_ratios *arm_clk_ratio) |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 31 | { |
| 32 | struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; |
| 33 | struct exynos5_mct_regs *mct_regs = |
| 34 | (struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE; |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 35 | u32 val, tmp; |
| 36 | |
| 37 | /* Turn on the MCT as early as possible. */ |
| 38 | mct_regs->g_tcon |= (1 << 8); |
| 39 | |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 40 | clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); |
| 41 | do { |
| 42 | val = readl(&clk->mux_stat_cpu); |
| 43 | } while ((val | MUX_APLL_SEL_MASK) != val); |
| 44 | |
| 45 | clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); |
| 46 | do { |
| 47 | val = readl(&clk->mux_stat_core1); |
| 48 | } while ((val | MUX_MPLL_SEL_MASK) != val); |
| 49 | |
| 50 | clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); |
| 51 | clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); |
| 52 | clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); |
| 53 | clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); |
| 54 | tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK |
| 55 | | MUX_GPLL_SEL_MASK; |
| 56 | do { |
| 57 | val = readl(&clk->mux_stat_top2); |
| 58 | } while ((val | tmp) != val); |
| 59 | |
| 60 | clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK); |
| 61 | do { |
| 62 | val = readl(&clk->mux_stat_cdrex); |
| 63 | } while ((val | MUX_BPLL_SEL_MASK) != val); |
| 64 | |
| 65 | /* PLL locktime */ |
| 66 | writel(APLL_LOCK_VAL, &clk->apll_lock); |
| 67 | |
| 68 | writel(MPLL_LOCK_VAL, &clk->mpll_lock); |
| 69 | |
| 70 | writel(BPLL_LOCK_VAL, &clk->bpll_lock); |
| 71 | |
| 72 | writel(CPLL_LOCK_VAL, &clk->cpll_lock); |
| 73 | |
| 74 | writel(GPLL_LOCK_VAL, &clk->gpll_lock); |
| 75 | |
| 76 | writel(EPLL_LOCK_VAL, &clk->epll_lock); |
| 77 | |
| 78 | writel(VPLL_LOCK_VAL, &clk->vpll_lock); |
| 79 | |
| 80 | writel(CLK_REG_DISABLE, &clk->pll_div2_sel); |
| 81 | |
| 82 | writel(MUX_HPM_SEL_MASK, &clk->src_cpu); |
| 83 | do { |
| 84 | val = readl(&clk->mux_stat_cpu); |
| 85 | } while ((val | HPM_SEL_SCLK_MPLL) != val); |
| 86 | |
| 87 | val = arm_clk_ratio->arm2_ratio << 28 |
| 88 | | arm_clk_ratio->apll_ratio << 24 |
| 89 | | arm_clk_ratio->pclk_dbg_ratio << 20 |
| 90 | | arm_clk_ratio->atb_ratio << 16 |
| 91 | | arm_clk_ratio->periph_ratio << 12 |
| 92 | | arm_clk_ratio->acp_ratio << 8 |
| 93 | | arm_clk_ratio->cpud_ratio << 4 |
| 94 | | arm_clk_ratio->arm_ratio; |
| 95 | writel(val, &clk->div_cpu0); |
| 96 | do { |
| 97 | val = readl(&clk->div_stat_cpu0); |
| 98 | } while (0 != val); |
| 99 | |
| 100 | writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); |
| 101 | do { |
| 102 | val = readl(&clk->div_stat_cpu1); |
| 103 | } while (0 != val); |
| 104 | |
| 105 | /* Set APLL */ |
| 106 | writel(APLL_CON1_VAL, &clk->apll_con1); |
| 107 | val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, |
| 108 | arm_clk_ratio->apll_sdiv); |
| 109 | writel(val, &clk->apll_con0); |
| 110 | while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) |
| 111 | ; |
| 112 | |
| 113 | /* Set MPLL */ |
| 114 | writel(MPLL_CON1_VAL, &clk->mpll_con1); |
| 115 | val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); |
| 116 | writel(val, &clk->mpll_con0); |
| 117 | while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) |
| 118 | ; |
| 119 | |
| 120 | /* |
| 121 | * Configure MUX_MPLL_FOUT to choose the direct clock source |
| 122 | * path and avoid the fixed DIV/2 block to save power |
| 123 | */ |
| 124 | setbits_le32(&clk->pll_div2_sel, MUX_MPLL_FOUT_SEL); |
| 125 | |
| 126 | /* Set BPLL */ |
| 127 | if (mem->use_bpll) { |
| 128 | writel(BPLL_CON1_VAL, &clk->bpll_con1); |
| 129 | val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); |
| 130 | writel(val, &clk->bpll_con0); |
| 131 | while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) |
| 132 | ; |
| 133 | |
| 134 | setbits_le32(&clk->pll_div2_sel, MUX_BPLL_FOUT_SEL); |
| 135 | } |
| 136 | |
| 137 | /* Set CPLL */ |
| 138 | writel(CPLL_CON1_VAL, &clk->cpll_con1); |
| 139 | val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); |
| 140 | writel(val, &clk->cpll_con0); |
| 141 | while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) |
| 142 | ; |
| 143 | |
| 144 | /* Set GPLL */ |
| 145 | writel(GPLL_CON1_VAL, &clk->gpll_con1); |
| 146 | val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); |
| 147 | writel(val, &clk->gpll_con0); |
| 148 | while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) |
| 149 | ; |
| 150 | |
| 151 | /* Set EPLL */ |
| 152 | writel(EPLL_CON2_VAL, &clk->epll_con2); |
| 153 | writel(EPLL_CON1_VAL, &clk->epll_con1); |
| 154 | val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); |
| 155 | writel(val, &clk->epll_con0); |
| 156 | while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) |
| 157 | ; |
| 158 | |
| 159 | /* Set VPLL */ |
| 160 | writel(VPLL_CON2_VAL, &clk->vpll_con2); |
| 161 | writel(VPLL_CON1_VAL, &clk->vpll_con1); |
| 162 | val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); |
| 163 | writel(val, &clk->vpll_con0); |
| 164 | while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) |
| 165 | ; |
| 166 | |
| 167 | writel(CLK_SRC_CORE0_VAL, &clk->src_core0); |
| 168 | writel(CLK_DIV_CORE0_VAL, &clk->div_core0); |
| 169 | while (readl(&clk->div_stat_core0) != 0) |
| 170 | ; |
| 171 | |
| 172 | writel(CLK_DIV_CORE1_VAL, &clk->div_core1); |
| 173 | while (readl(&clk->div_stat_core1) != 0) |
| 174 | ; |
| 175 | |
| 176 | writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt); |
| 177 | while (readl(&clk->div_stat_sysrgt) != 0) |
| 178 | ; |
| 179 | |
| 180 | writel(CLK_DIV_ACP_VAL, &clk->div_acp); |
| 181 | while (readl(&clk->div_stat_acp) != 0) |
| 182 | ; |
| 183 | |
| 184 | writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft); |
| 185 | while (readl(&clk->div_stat_syslft) != 0) |
| 186 | ; |
| 187 | |
| 188 | writel(CLK_SRC_TOP0_VAL, &clk->src_top0); |
| 189 | writel(CLK_SRC_TOP1_VAL, &clk->src_top1); |
| 190 | writel(TOP2_VAL, &clk->src_top2); |
| 191 | writel(CLK_SRC_TOP3_VAL, &clk->src_top3); |
| 192 | |
| 193 | writel(CLK_DIV_TOP0_VAL, &clk->div_top0); |
| 194 | while (readl(&clk->div_stat_top0)) |
| 195 | ; |
| 196 | |
| 197 | writel(CLK_DIV_TOP1_VAL, &clk->div_top1); |
| 198 | while (readl(&clk->div_stat_top1)) |
| 199 | ; |
| 200 | |
| 201 | writel(CLK_SRC_LEX_VAL, &clk->src_lex); |
| 202 | while (1) { |
| 203 | val = readl(&clk->mux_stat_lex); |
| 204 | if (val == (val | 1)) |
| 205 | break; |
| 206 | } |
| 207 | |
| 208 | writel(CLK_DIV_LEX_VAL, &clk->div_lex); |
| 209 | while (readl(&clk->div_stat_lex)) |
| 210 | ; |
| 211 | |
| 212 | writel(CLK_DIV_R0X_VAL, &clk->div_r0x); |
| 213 | while (readl(&clk->div_stat_r0x)) |
| 214 | ; |
| 215 | |
| 216 | writel(CLK_DIV_R0X_VAL, &clk->div_r0x); |
| 217 | while (readl(&clk->div_stat_r0x)) |
| 218 | ; |
| 219 | |
| 220 | writel(CLK_DIV_R1X_VAL, &clk->div_r1x); |
| 221 | while (readl(&clk->div_stat_r1x)) |
| 222 | ; |
| 223 | |
| 224 | if (mem->use_bpll) { |
| 225 | writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL | |
| 226 | MUX_MCLK_DPHY_SEL, &clk->src_cdrex); |
| 227 | } else { |
| 228 | writel(CLK_REG_DISABLE, &clk->src_cdrex); |
| 229 | } |
| 230 | |
| 231 | writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex); |
| 232 | while (readl(&clk->div_stat_cdrex)) |
| 233 | ; |
| 234 | |
| 235 | val = readl(&clk->src_cpu); |
| 236 | val |= CLK_SRC_CPU_VAL; |
| 237 | writel(val, &clk->src_cpu); |
| 238 | |
| 239 | val = readl(&clk->src_top2); |
| 240 | val |= CLK_SRC_TOP2_VAL; |
| 241 | writel(val, &clk->src_top2); |
| 242 | |
| 243 | val = readl(&clk->src_core1); |
| 244 | val |= CLK_SRC_CORE1_VAL; |
| 245 | writel(val, &clk->src_core1); |
| 246 | |
| 247 | writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys); |
| 248 | writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0); |
| 249 | while (readl(&clk->div_stat_fsys0)) |
| 250 | ; |
| 251 | |
| 252 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu); |
| 253 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_core); |
| 254 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp); |
| 255 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_top); |
| 256 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex); |
| 257 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x); |
| 258 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x); |
| 259 | writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex); |
| 260 | |
| 261 | writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0); |
| 262 | writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0); |
| 263 | |
| 264 | writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1); |
| 265 | writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1); |
| 266 | writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2); |
| 267 | writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp); |
| 268 | writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); |
| 269 | writel(CLK_DIV_ISP0_VAL, &clk->div_isp0); |
| 270 | writel(CLK_DIV_ISP1_VAL, &clk->div_isp1); |
| 271 | writel(CLK_DIV_ISP2_VAL, &clk->div_isp2); |
| 272 | |
| 273 | /* FIMD1 SRC CLK SELECTION */ |
| 274 | writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0); |
| 275 | |
| 276 | val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET |
| 277 | | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET |
| 278 | | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET |
| 279 | | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET; |
| 280 | writel(val, &clk->div_fsys2); |
| 281 | } |
| 282 | |
| 283 | void clock_gate(void) |
| 284 | { |
| 285 | struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; |
| 286 | |
| 287 | /* CLK_GATE_IP_SYSRGT */ |
| 288 | clrbits_le32(&clk->gate_ip_sysrgt, CLK_C2C_MASK); |
| 289 | |
| 290 | /* CLK_GATE_IP_ACP */ |
| 291 | clrbits_le32(&clk->gate_ip_acp, CLK_SMMUG2D_MASK | |
| 292 | CLK_SMMUSSS_MASK | |
| 293 | CLK_SMMUMDMA_MASK | |
| 294 | CLK_ID_REMAPPER_MASK | |
| 295 | CLK_G2D_MASK | |
| 296 | CLK_SSS_MASK | |
| 297 | CLK_MDMA_MASK | |
| 298 | CLK_SECJTAG_MASK); |
| 299 | |
| 300 | /* CLK_GATE_BUS_SYSLFT */ |
| 301 | clrbits_le32(&clk->gate_bus_syslft, CLK_EFCLK_MASK); |
| 302 | |
| 303 | /* CLK_GATE_IP_ISP0 */ |
| 304 | clrbits_le32(&clk->gate_ip_isp0, CLK_UART_ISP_MASK | |
| 305 | CLK_WDT_ISP_MASK | |
| 306 | CLK_PWM_ISP_MASK | |
| 307 | CLK_MTCADC_ISP_MASK | |
| 308 | CLK_I2C1_ISP_MASK | |
| 309 | CLK_I2C0_ISP_MASK | |
| 310 | CLK_MPWM_ISP_MASK | |
| 311 | CLK_MCUCTL_ISP_MASK | |
| 312 | CLK_INT_COMB_ISP_MASK | |
| 313 | CLK_SMMU_MCUISP_MASK | |
| 314 | CLK_SMMU_SCALERP_MASK | |
| 315 | CLK_SMMU_SCALERC_MASK | |
| 316 | CLK_SMMU_FD_MASK | |
| 317 | CLK_SMMU_DRC_MASK | |
| 318 | CLK_SMMU_ISP_MASK | |
| 319 | CLK_GICISP_MASK | |
| 320 | CLK_ARM9S_MASK | |
| 321 | CLK_MCUISP_MASK | |
| 322 | CLK_SCALERP_MASK | |
| 323 | CLK_SCALERC_MASK | |
| 324 | CLK_FD_MASK | |
| 325 | CLK_DRC_MASK | |
| 326 | CLK_ISP_MASK); |
| 327 | |
| 328 | /* CLK_GATE_IP_ISP1 */ |
| 329 | clrbits_le32(&clk->gate_ip_isp1, CLK_SPI1_ISP_MASK | |
| 330 | CLK_SPI0_ISP_MASK | |
| 331 | CLK_SMMU3DNR_MASK | |
| 332 | CLK_SMMUDIS1_MASK | |
| 333 | CLK_SMMUDIS0_MASK | |
| 334 | CLK_SMMUODC_MASK | |
| 335 | CLK_3DNR_MASK | |
| 336 | CLK_DIS_MASK | |
| 337 | CLK_ODC_MASK); |
| 338 | |
| 339 | /* CLK_GATE_SCLK_ISP */ |
| 340 | clrbits_le32(&clk->gate_sclk_isp, SCLK_MPWM_ISP_MASK); |
| 341 | |
| 342 | /* CLK_GATE_IP_GSCL */ |
| 343 | clrbits_le32(&clk->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK | |
| 344 | CLK_SMMUFIMC_LITE1_MASK | |
| 345 | CLK_SMMUFIMC_LITE0_MASK | |
| 346 | CLK_SMMUGSCL3_MASK | |
| 347 | CLK_SMMUGSCL2_MASK | |
| 348 | CLK_SMMUGSCL1_MASK | |
| 349 | CLK_SMMUGSCL0_MASK | |
| 350 | CLK_GSCL_WRAP_B_MASK | |
| 351 | CLK_GSCL_WRAP_A_MASK | |
| 352 | CLK_CAMIF_TOP_MASK | |
| 353 | CLK_GSCL3_MASK | |
| 354 | CLK_GSCL2_MASK | |
| 355 | CLK_GSCL1_MASK | |
| 356 | CLK_GSCL0_MASK); |
| 357 | |
| 358 | /* CLK_GATE_IP_DISP1 */ |
| 359 | clrbits_le32(&clk->gate_ip_disp1, CLK_SMMUTVX_MASK | |
| 360 | CLK_ASYNCTVX_MASK | |
| 361 | CLK_HDMI_MASK | |
| 362 | CLK_MIXER_MASK | |
| 363 | CLK_DSIM1_MASK); |
| 364 | |
| 365 | /* CLK_GATE_IP_MFC */ |
| 366 | clrbits_le32(&clk->gate_ip_mfc, CLK_SMMUMFCR_MASK | |
| 367 | CLK_SMMUMFCL_MASK | |
| 368 | CLK_MFC_MASK); |
| 369 | |
| 370 | /* CLK_GATE_IP_GEN */ |
| 371 | clrbits_le32(&clk->gate_ip_gen, CLK_SMMUMDMA1_MASK | |
| 372 | CLK_SMMUJPEG_MASK | |
| 373 | CLK_SMMUROTATOR_MASK | |
| 374 | CLK_MDMA1_MASK | |
| 375 | CLK_JPEG_MASK | |
| 376 | CLK_ROTATOR_MASK); |
| 377 | |
| 378 | /* CLK_GATE_IP_FSYS */ |
| 379 | clrbits_le32(&clk->gate_ip_fsys, CLK_WDT_IOP_MASK | |
| 380 | CLK_SMMUMCU_IOP_MASK | |
| 381 | CLK_SATA_PHY_I2C_MASK | |
| 382 | CLK_SATA_PHY_CTRL_MASK | |
| 383 | CLK_MCUCTL_MASK | |
| 384 | CLK_NFCON_MASK | |
| 385 | CLK_SMMURTIC_MASK | |
| 386 | CLK_RTIC_MASK | |
| 387 | CLK_MIPI_HSI_MASK | |
| 388 | CLK_USBOTG_MASK | |
| 389 | CLK_SATA_MASK | |
| 390 | CLK_PDMA1_MASK | |
| 391 | CLK_PDMA0_MASK | |
| 392 | CLK_MCU_IOP_MASK); |
| 393 | |
| 394 | /* CLK_GATE_IP_PERIC */ |
| 395 | clrbits_le32(&clk->gate_ip_peric, CLK_HS_I2C3_MASK | |
| 396 | CLK_HS_I2C2_MASK | |
| 397 | CLK_HS_I2C1_MASK | |
| 398 | CLK_HS_I2C0_MASK | |
| 399 | CLK_AC97_MASK | |
| 400 | CLK_SPDIF_MASK | |
| 401 | CLK_PCM2_MASK | |
| 402 | CLK_PCM1_MASK | |
| 403 | CLK_I2S2_MASK | |
| 404 | CLK_SPI2_MASK | |
| 405 | CLK_SPI0_MASK); |
| 406 | |
David Hendricks | aee444f | 2013-04-22 16:03:11 -0700 | [diff] [blame] | 407 | /* |
| 408 | * CLK_GATE_IP_PERIS |
| 409 | * Note: Keep CHIPID_APBIF ungated to ensure reading the product ID |
| 410 | * register (PRO_ID) works correctly when the OS kernel determines |
| 411 | * which chip it is running on. |
| 412 | */ |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 413 | clrbits_le32(&clk->gate_ip_peris, CLK_RTC_MASK | |
| 414 | CLK_TZPC9_MASK | |
| 415 | CLK_TZPC8_MASK | |
| 416 | CLK_TZPC7_MASK | |
| 417 | CLK_TZPC6_MASK | |
| 418 | CLK_TZPC5_MASK | |
| 419 | CLK_TZPC4_MASK | |
| 420 | CLK_TZPC3_MASK | |
| 421 | CLK_TZPC2_MASK | |
| 422 | CLK_TZPC1_MASK | |
David Hendricks | aee444f | 2013-04-22 16:03:11 -0700 | [diff] [blame] | 423 | CLK_TZPC0_MASK); |
Stefan Reinauer | 9fe20cb | 2012-12-07 17:18:43 -0800 | [diff] [blame] | 424 | |
| 425 | /* CLK_GATE_BLOCK */ |
| 426 | clrbits_le32(&clk->gate_block, CLK_ACP_MASK); |
| 427 | |
| 428 | /* CLK_GATE_IP_CDREX */ |
| 429 | clrbits_le32(&clk->gate_ip_cdrex, CLK_DPHY0_MASK | |
| 430 | CLK_DPHY1_MASK | |
| 431 | CLK_TZASC_DRBXR_MASK); |
| 432 | |
| 433 | } |
| 434 | |
| 435 | void clock_init_dp_clock(void) |
| 436 | { |
| 437 | struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE; |
| 438 | |
| 439 | /* DP clock enable */ |
| 440 | setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW); |
| 441 | |
| 442 | /* We run DP at 267 Mhz */ |
| 443 | setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); |
| 444 | } |
| 445 | |