| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2008-2009 coresystems GmbH |
| * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. |
| * Copyright (C) 2013-2015 Sage Electronic Engineering, LLC. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #ifndef SOUTHBRIDGE_INTEL_I89XX_PCH_H |
| #define SOUTHBRIDGE_INTEL_I89XX_PCH_H |
| |
| #include <arch/acpi.h> |
| |
| /* PCH types */ |
| #define PCH_TYPE_CC 0x23 /* CaveCreek */ |
| |
| /* PCH stepping values for LPC device */ |
| #define PCH_STEP_A0 0 |
| #define PCH_STEP_A1 1 |
| #define PCH_STEP_B0 2 |
| #define PCH_STEP_B1 3 |
| #define PCH_STEP_B2 4 |
| #define PCH_STEP_B3 5 |
| |
| /* |
| * It does not matter where we put the SMBus I/O base, as long as we |
| * keep it consistent and don't interfere with other devices. Stage2 |
| * will relocate this anyways. |
| * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE |
| * again. But handling static BARs is a generic problem that should be |
| * solved in the device allocator. |
| */ |
| #define SMBUS_IO_BASE 0x0500 |
| #define SMBUS_SLAVE_ADDR 0x24 |
| /* TODO Make sure these don't get changed by stage2 */ |
| #define DEFAULT_GPIOBASE 0x0480 |
| #define DEFAULT_PMBASE 0x0400 |
| |
| #ifndef __ACPI__ |
| #define DEFAULT_RCBA ((u8 *)0xfed1c000) |
| #else |
| #define DEFAULT_RCBA 0xfed1c000 |
| #endif |
| |
| #ifndef __ACPI__ |
| #define DEBUG_PERIODIC_SMIS 0 |
| |
| #if defined (__SMM__) && !defined(__ASSEMBLER__) |
| void intel_pch_finalize_smm(void); |
| #endif |
| |
| #if !defined(__ASSEMBLER__) && !defined(__ROMCC__) |
| #if !defined(__PRE_RAM__) && !defined(__SMM__) |
| #include "chip.h" |
| int pch_silicon_revision(void); |
| int pch_silicon_type(void); |
| int pch_silicon_supported(int type, int rev); |
| void pch_enable(device_t dev); |
| #if IS_ENABLED(CONFIG_ELOG) |
| void pch_log_state(void); |
| #endif |
| #else |
| /* writes an address and one byte of data */ |
| s16 smbus_write_single_byte(u8 device, u8 address, u8 data); |
| |
| /* Sends an address and reads one byte of data */ |
| int smbus_read_byte(unsigned device, unsigned address); |
| |
| /* writes a single byte of data to smbus without an address byte */ |
| s16 smbus_quick_write(u8 device, u8 data); |
| |
| /* gets one byte of data from smbus without writing an address. */ |
| s16 smbus_quick_read(u8 device); |
| |
| void enable_smbus(void); |
| void enable_usb_bar(void); |
| int early_spi_read(u32 offset, u32 size, u8 *buffer); |
| void sandybridge_sb_early_initialization(void); |
| void early_pch_init(void); |
| #endif |
| #endif |
| |
| #define MAINBOARD_POWER_OFF 0 |
| #define MAINBOARD_POWER_ON 1 |
| #define MAINBOARD_POWER_KEEP 2 |
| |
| #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON |
| #endif |
| |
| #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) |
| #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) |
| #define PCH_PCIE_DEV_SLOT 28 |
| |
| /* PCI Configuration Space (D31:F0): LPC */ |
| #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) |
| #define SERIRQ_CNTL 0x64 |
| |
| #define GEN_PMCON_1 0xa0 |
| #define GEN_PMCON_2 0xa2 |
| #define GEN_PMCON_3 0xa4 |
| #define ETR3 0xac |
| #define ETR3_CWORWRE (1 << 18) |
| #define ETR3_CF9GR (1 << 20) |
| |
| /* GEN_PMCON_3 bits */ |
| #define RTC_BATTERY_DEAD (1 << 2) |
| #define RTC_POWER_FAILED (1 << 1) |
| #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| |
| #define PMBASE 0x40 |
| #define ACPI_CNTL 0x44 |
| #define BIOS_CNTL 0xDC |
| #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ |
| #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ |
| #define GPIO_ROUT 0xb8 |
| |
| /* PIRQ[A-H] Routing registers */ |
| #define PIRQA_ROUT 0x60 |
| #define PIRQB_ROUT 0x61 |
| #define PIRQC_ROUT 0x62 |
| #define PIRQD_ROUT 0x63 |
| #define PIRQE_ROUT 0x68 |
| #define PIRQF_ROUT 0x69 |
| #define PIRQG_ROUT 0x6A |
| #define PIRQH_ROUT 0x6B |
| |
| #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ |
| #define LPC_EN 0x82 /* LPC IF Enables Register */ |
| #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ |
| #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ |
| #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ |
| #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ |
| #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ |
| #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ |
| #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ |
| #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ |
| #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ |
| #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ |
| #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ |
| #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ |
| #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ |
| #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ |
| |
| /* PCI Configuration Space (D31:F2/5) */ |
| #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) |
| #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) |
| #define INTR_LN 0x3c |
| #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ |
| #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ |
| #define SATA_SP 0xd0 /* Scratchpad */ |
| |
| /* SATA IOBP Registers */ |
| #define SATA_IOBP_SP0G3IR 0xea000151 |
| #define SATA_IOBP_SP1G3IR 0xea000051 |
| |
| /* PCI Configuration Space (D31:F3): SMBus */ |
| #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) |
| #define SMB_BASE 0x20 |
| #define HOSTC 0x40 |
| #define SMB_RCV_SLVA 0x09 |
| |
| /* HOSTC bits */ |
| #define I2C_EN (1 << 2) |
| #define SMB_SMI_EN (1 << 1) |
| #define HST_EN (1 << 0) |
| |
| /* Southbridge IO BARs */ |
| |
| #define GPIOBASE 0x48 |
| |
| #define PMBASE 0x40 |
| |
| /* Root Complex Register Block */ |
| #define RCBA 0xf0 |
| |
| #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x)) |
| #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x)) |
| #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x)) |
| |
| #define RCBA_AND_OR(bits, x, and, or) \ |
| RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or)) |
| #define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or) |
| #define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or) |
| #define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or) |
| #define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or) |
| |
| #define V0CTL 0x0014 /* 32bit */ |
| #define V0STS 0x001a /* 16bit */ |
| |
| #define V1CAP 0x001c /* 32bit */ |
| #define V1CTL 0x0020 /* 32bit */ |
| #define V1STS 0x0026 /* 16bit */ |
| |
| #define RPC 0x0224 /* 32bit */ |
| #define RPFN 0x0238 /* 32bit */ |
| |
| /* Root Port configuratinon space hide */ |
| #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) |
| /* Get the function number assigned to a Root Port */ |
| #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) |
| /* Set the function number for a Root Port */ |
| #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) |
| /* Root Port function number mask */ |
| #define RPFN_FNMASK(port) (7 << ((port) * 4)) |
| |
| #define TRSR 0x1e00 /* 8bit */ |
| #define TRCR 0x1e10 /* 64bit */ |
| #define TWDR 0x1e18 /* 64bit */ |
| |
| #define TCTL 0x3000 /* 8bit */ |
| |
| /* IO Buffer Programming */ |
| #define IOBPIRI 0x2330 |
| #define IOBPD 0x2334 |
| #define IOBPS 0x2338 |
| #define IOBPS_RW_BX ((1 << 9)|(1 << 10)) |
| #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) |
| #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) |
| |
| /* |
| * Interrupt Pin (IP) and Interrupt Route (IR) |
| * registers |
| */ |
| #define D31IP 0x3100 /* 32bit */ |
| #define D31IP_TTIP 24 /* Thermal Throttle Pin */ |
| #define D31IP_SIP2 20 /* SATA Pin 2 */ |
| #define D31IP_SMIP 12 /* SMBUS Pin */ |
| #define D31IP_SIP 8 /* SATA Pin */ |
| #define D29IP 0x3108 /* 32bit */ |
| #define D29IP_E1P 0 /* EHCI #1 Pin */ |
| #define D28IP 0x310c /* 32bit */ |
| #define D28IP_P4IP 12 /* PCI Express Port 4 */ |
| #define D28IP_P3IP 8 /* PCI Express Port 3 */ |
| #define D28IP_P2IP 4 /* PCI Express Port 2 */ |
| #define D28IP_P1IP 0 /* PCI Express Port 1 */ |
| #define D22IP 0x3124 /* 32bit */ |
| #define D22IP_KTIP 12 /* KT Pin */ |
| #define D22IP_IDERIP 8 /* IDE-R Pin */ |
| #define D22IP_MEI2IP 4 /* MEI #2 Pin */ |
| #define D22IP_MEI1IP 0 /* MEI #1 Pin */ |
| #define D31IR 0x3140 /* 16bit */ |
| #define D29IR 0x3144 /* 16bit */ |
| #define D28IR 0x3146 /* 16bit */ |
| #define D22IR 0x315c /* 16bit */ |
| #define OIC 0x31fe /* 16bit */ |
| #define SOFT_RESET_CTRL 0x38f4 |
| #define SOFT_RESET_DATA 0x38f8 |
| |
| #if !defined(__ASSEMBLER__) |
| #define NUM_IR_DEVS 32 |
| |
| /* Certain device numbers have Interrupt registers in the RCBA */ |
| #define PCH_ALLOWED_IRQ_DEVNUM 0xB0400000 /* 31, 29, 28, 22 */ |
| |
| /* |
| * Some devices have specific IRQ registers in |
| * the LPC for interrupt control |
| */ |
| struct dev_irq_regs { |
| uint32_t ip_reg; /* Interrupt Pin register */ |
| uint32_t ir_reg; /* Interrupt Route register */ |
| }; |
| |
| /* |
| * Certain PCH device numbers have specific IRQ registers |
| * associated with them (D(x)IP / D(x)IR) for Interrupt Pin |
| * and Interrupt Routing information. |
| */ |
| static const struct dev_irq_regs irq_regs[NUM_IR_DEVS] = { |
| [31] = {D31IP, D31IR}, |
| [29] = {D29IP, D29IR}, |
| [28] = {D28IP, D28IR}, |
| [22] = {D22IP, D22IR}, |
| }; |
| #endif |
| |
| #define RC 0x3400 /* 32bit */ |
| #define HPTC 0x3404 /* 32bit */ |
| #define GCS 0x3410 /* 32bit */ |
| #define BUC 0x3414 /* 32bit */ |
| #define PCH_DISABLE_GBE (1 << 5) |
| #define FD 0x3418 /* 32bit */ |
| #define DISPBDF 0x3424 /* 16bit */ |
| #define FD2 0x3428 /* 32bit */ |
| #define CG 0x341c /* 32bit */ |
| |
| /* Function Disable 1 RCBA 0x3418 */ |
| #define PCH_DISABLE_ALWAYS 0 |
| #define PCH_DISABLE_SATA1 (1 << 2) |
| #define PCH_DISABLE_SMBUS (1 << 3) |
| #define PCH_DISABLE_LPC (1 << 14) |
| #define PCH_DISABLE_EHCI1 (1 << 15) |
| #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) |
| #define PCH_DISABLE_THERMAL (1 << 24) |
| #define PCH_DISABLE_SATA2 (1 << 25) |
| |
| /* Function Disable 2 RCBA 0x3428 */ |
| #define PCH_DISABLE_KT (1 << 4) |
| #define PCH_DISABLE_IDER (1 << 3) |
| #define PCH_DISABLE_MEI2 (1 << 2) |
| #define PCH_DISABLE_MEI1 (1 << 1) |
| |
| /* ICH7 GPIOBASE */ |
| #define GPIO_USE_SEL 0x00 |
| #define GP_IO_SEL 0x04 |
| #define GP_LVL 0x0c |
| #define GPO_BLINK 0x18 |
| #define GPI_INV 0x2c |
| #define GPIO_USE_SEL2 0x30 |
| #define GP_IO_SEL2 0x34 |
| #define GP_LVL2 0x38 |
| #define GPIO_USE_SEL3 0x40 |
| #define GP_IO_SEL3 0x44 |
| #define GP_LVL3 0x48 |
| #define GP_RST_SEL1 0x60 |
| #define GP_RST_SEL2 0x64 |
| #define GP_RST_SEL3 0x68 |
| |
| /* ICH7 PMBASE */ |
| #define PM1_STS 0x00 |
| #define WAK_STS (1 << 15) |
| #define PCIEXPWAK_STS (1 << 14) |
| #define PRBTNOR_STS (1 << 11) |
| #define RTC_STS (1 << 10) |
| #define PWRBTN_STS (1 << 8) |
| #define GBL_STS (1 << 5) |
| #define BM_STS (1 << 4) |
| #define TMROF_STS (1 << 0) |
| #define PM1_EN 0x02 |
| #define PCIEXPWAK_DIS (1 << 14) |
| #define RTC_EN (1 << 10) |
| #define PWRBTN_EN (1 << 8) |
| #define GBL_EN (1 << 5) |
| #define TMROF_EN (1 << 0) |
| #define PM1_CNT 0x04 |
| #define GBL_RLS (1 << 2) |
| #define BM_RLD (1 << 1) |
| #define SCI_EN (1 << 0) |
| #define PM1_TMR 0x08 |
| #define PROC_CNT 0x10 |
| #define LV2 0x14 |
| #define LV3 0x15 |
| #define LV4 0x16 |
| #define PM2_CNT 0x50 // mobile only |
| #define GPE0_STS 0x20 |
| #define PME_B0_STS (1 << 13) |
| #define PME_STS (1 << 11) |
| #define BATLOW_STS (1 << 10) |
| #define PCI_EXP_STS (1 << 9) |
| #define RI_STS (1 << 8) |
| #define SMB_WAK_STS (1 << 7) |
| #define TCOSCI_STS (1 << 6) |
| #define SWGPE_STS (1 << 2) |
| #define HOT_PLUG_STS (1 << 1) |
| #define GPE0_EN 0x28 |
| #define PME_B0_EN (1 << 13) |
| #define PME_EN (1 << 11) |
| #define TCOSCI_EN (1 << 6) |
| #define SMI_EN 0x30 |
| #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic |
| #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic |
| #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS |
| #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) |
| #define MCSMI_EN (1 << 11) // Trap microcontroller range access |
| #define BIOS_RLS (1 << 7) // asserts SCI on bit set |
| #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set |
| #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# |
| #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# |
| #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic |
| #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit |
| #define EOS (1 << 1) // End of SMI (deassert SMI#) |
| #define GBL_SMI_EN (1 << 0) // SMI# generation at all? |
| #define SMI_STS 0x34 |
| #define ALT_GP_SMI_EN 0x38 |
| #define ALT_GP_SMI_STS 0x3a |
| #define GPE_CNTL 0x42 |
| #define DEVACT_STS 0x44 |
| #define SS_CNT 0x50 |
| #define C3_RES 0x54 |
| #define TCO1_STS 0x64 |
| #define DMISCI_STS (1 << 9) |
| #define TCO2_STS 0x66 |
| |
| /* |
| * SPI Opcode Menu setup for SPIBAR lockdown |
| * should support most common flash chips. |
| */ |
| |
| #define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ |
| #define SPI_OPTYPE_0 0x01 /* Write, no address */ |
| |
| #define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ |
| #define SPI_OPTYPE_1 0x03 /* Write, address required */ |
| |
| #define SPI_OPMENU_2 0x03 /* READ: Read Data */ |
| #define SPI_OPTYPE_2 0x02 /* Read, address required */ |
| |
| #define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ |
| #define SPI_OPTYPE_3 0x00 /* Read, no address */ |
| |
| #define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ |
| #define SPI_OPTYPE_4 0x03 /* Write, address required */ |
| |
| #define SPI_OPMENU_5 0x9f /* RDID: Read ID */ |
| #define SPI_OPTYPE_5 0x00 /* Read, no address */ |
| |
| #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ |
| #define SPI_OPTYPE_6 0x03 /* Write, address required */ |
| |
| #define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ |
| #define SPI_OPTYPE_7 0x02 /* Read, address required */ |
| |
| #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ |
| (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) |
| #define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ |
| (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) |
| |
| #define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ |
| (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ |
| (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ |
| (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) |
| |
| #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ |
| |
| #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ |
| #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ |
| #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ |
| #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ |
| #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ |
| #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ |
| #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) |
| #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ |
| #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ |
| #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ |
| #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ |
| #define SPIBAR_FADDR 0x3808 /* SPI flash address */ |
| #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ |
| |
| #endif /* __ACPI__ */ |
| #endif /* SOUTHBRIDGE_INTEL_I89XX_PCH_H */ |