mb/system76/{tgl,skl}/dt: Use comma separated list for arrays
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.
Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.
While on it, remove superfluous comments related to modified lines.
Change-Id: I75aeb46ea3b4a7c0a41dce375735e7b42ed59587
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78664
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb
index bcd1130..3b84d7f 100644
--- a/src/mainboard/system76/kbl-u/devicetree.cb
+++ b/src/mainboard/system76/kbl-u/devicetree.cb
@@ -110,26 +110,30 @@
device ref igpu on end
device ref sa_thermal on end
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right
- register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
- register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
- register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
- register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left
- register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port right */
+ [1] = USB2_PORT_FLEX(OC_SKIP), /* 3G / LTE */
+ [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port right */
+ [3] = USB2_PORT_FLEX(OC_SKIP), /* Camera */
+ [4] = USB2_PORT_FLEX(OC_SKIP), /* Bluetooth */
+ [6] = USB2_PORT_FLEX(OC_SKIP), /* Type-A port left */
+ [7] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port right */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port right */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type C port right */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port left */
+ }"
end
device ref thermal on end
device ref sata on
register "SataSalpSupport" = "0"
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[2]" = "1"
register "SataSpeedLimit" = "2"
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [2] = 1,
+ }"
end
device ref pcie_rp1 on
# Root port #1 x4 (TBT)
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
index 58cf708..d03bd2e 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
@@ -29,23 +29,27 @@
register "PcieClkSrcClkReq[4]" = "4"
end
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right)
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left)
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right)
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right) */
+ [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [4] = USB2_PORT_MID(OC_SKIP), /* USB 2.0 (Left) */
+ [5] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 (Right) */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Right) */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ }"
end
device ref sata on
- register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
- register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+ register "SataPortsEnable" = "{
+ [0] = 1, /* HDD (SATA0B) */
+ [1] = 1, /* SSD1 (SATA1A) */
+ }"
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 5 (GLAN)
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
index 7bcb51c..b463fe7 100644
--- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
@@ -29,23 +29,27 @@
register "PcieClkSrcClkReq[7]" = "7"
end
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 2 (Right)
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back)
- register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left)
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right)
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back)
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 2 (Right) */
+ [1] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [2] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.2 Gen 2 Type C (Back) */
+ [5] = USB2_PORT_MID(OC_SKIP), /* USB 2.0 (Left) */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [8] = USB2_PORT_MID(OC_SKIP), /* Per-Key */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 (Right) */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 2 Type C (Back) */
+ }"
end
device ref sata on
- register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
- register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
+ register "SataPortsEnable" = "{
+ [0] = 1, /* HDD (SATA0B) */
+ [1] = 1, /* SSD2 (SATA1A) */
+ }"
end
device ref pcie_rp5 on
# PCIe root port #5 x1, Clock 8 (GLAN)
diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
index 87311d9..6f25d7b 100644
--- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
+++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb
@@ -41,19 +41,21 @@
end
device ref tbt_dma0 on end # TYPEC1
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
- register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
- register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 1)
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Right 2)
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [2] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right 1) */
+ [3] = USB2_PORT_MID(OC_SKIP), /* USB 3.2 Gen 1 (Right 2) */
+ [4] = USB2_PORT_MID(OC_SKIP), /* Per-Key */
+ [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [8] = USB2_PORT_TYPE_C(OC_SKIP), /* TYPEC1 */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Left) */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Right 1) */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.2 Gen 1 (Right 2) */
+ }"
end
device ref sata on
register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
index 8e05677..9a669ef 100644
--- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
@@ -51,18 +51,20 @@
end
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # UJ_USB1
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* UJ_USB1 */
+ [1] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 */
+ [2] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */
+ [4] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [5] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC2 */
+ [6] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH0 */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH1 */
+ }"
# ACPI
chip drivers/usb/acpi
diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
index 1b4249c..7c3475e 100644
--- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb
@@ -51,19 +51,21 @@
end
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2
- register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
- register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
- register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH0
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* J_USB3_2 */
+ [1] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 */
+ [2] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */
+ [4] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
+ [5] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC2 */
+ [6] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_2 */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH0 */
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_TYPEC1 CH1 */
+ }"
# ACPI
chip drivers/usb/acpi
device ref xhci_root_hub on
diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
index 3be5b5c..671cdc4 100644
--- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
+++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
@@ -52,15 +52,17 @@
end
device ref south_xhci on
- # USB2
- register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1
- register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2
- register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera
- register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- # USB3
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_1
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB3_2
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC_SKIP), /* J_USB3_1 */
+ [1] = USB2_PORT_MID(OC_SKIP), /* J_USB3_2 */
+ [2] = USB2_PORT_TYPE_C(OC_SKIP), /* J_TYPEC1 */
+ [6] = USB2_PORT_MID(OC_SKIP), /* Camera */
+ [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_1 */
+ [1] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB3_2 */
+ }"
# ACPI
chip drivers/usb/acpi
device ref xhci_root_hub on