| chip soc/intel/tigerlake |
| device domain 0 on |
| subsystemid 0x1558 0x50e1 inherit |
| |
| device ref peg1 on |
| # PCIe PEG1 x16, Clock 9 (DGPU) |
| register "PcieClkSrcUsage[9]" = "0x41" |
| register "PcieClkSrcClkReq[9]" = "9" |
| chip soc/intel/common/block/pcie/rtd3 |
| register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH |
| register "enable_delay_ms" = "16" |
| register "enable_off_delay_ms" = "4" |
| register "reset_delay_ms" = "10" |
| register "reset_off_delay_ms" = "4" |
| register "srcclk_pin" = "9" # PEG_CLKREQ# |
| device generic 0 on end |
| end |
| end |
| device ref igpu on |
| # DDIB is HDMI |
| register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP" |
| register "DdiPortBHpd" = "1" |
| register "DdiPortBDdc" = "1" |
| end |
| device ref peg0 on |
| # PCIe PEG0 x4, Clock 7 (SSD1) |
| register "PcieClkSrcUsage[7]" = "0x40" |
| register "PcieClkSrcClkReq[7]" = "7" |
| end |
| device ref south_xhci on |
| # USB2 |
| register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 2 (Right) |
| register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left) |
| register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back) |
| register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left) |
| register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera |
| register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key |
| register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint |
| register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| # USB3 |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right) |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left) |
| register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back) |
| end |
| device ref sata on |
| register "SataPortsEnable[0]" = "1" # HDD (SATA0B) |
| register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A) |
| end |
| device ref pcie_rp5 on |
| # PCIe root port #5 x1, Clock 8 (GLAN) |
| register "PcieRpEnable[4]" = "1" |
| register "PcieRpLtrEnable[4]" = "1" |
| #register "PcieClkSrcUsage[8]" = "4" |
| register "PcieClkSrcClkReq[8]" = "8" |
| end |
| device ref pcie_rp7 on |
| # PCIe root port #7 x1, Clock 3 (CARD) |
| register "PcieRpEnable[6]" = "1" |
| register "PcieRpLtrEnable[6]" = "1" |
| register "PcieClkSrcUsage[3]" = "6" |
| register "PcieClkSrcClkReq[3]" = "3" |
| end |
| device ref pcie_rp8 on |
| # PCIe root port #8 x1, Clock 2 (WLAN) |
| register "PcieRpEnable[7]" = "1" |
| register "PcieRpLtrEnable[7]" = "1" |
| register "PcieClkSrcUsage[2]" = "7" |
| register "PcieClkSrcClkReq[2]" = "2" |
| register "PcieRpSlotImplemented[7]" = "1" |
| end |
| device ref pcie_rp9 on |
| # PCIe root port #9 x4, Clock 10 (SSD2) |
| register "PcieRpEnable[8]" = "1" |
| register "PcieRpLtrEnable[8]" = "1" |
| register "PcieClkSrcUsage[10]" = "8" |
| register "PcieClkSrcClkReq[10]" = "10" |
| register "PcieRpSlotImplemented[8]" = "1" |
| end |
| device ref gbe on end |
| end |
| end |