nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree
Transfer all USB responsibilities to southbridge/intel/bd82x6x,
using one set of USB port configuration supplied by mainboards
in the southbridge section of their devicetree.
For MRC raminit, export southbridge_fill_pei_data() as a hook for
southbridge code to implement. With new code via this hook, bd82x6x
fills pei_data based on this one set of USB port config.
For native raminit, early_usb_init() now goes directly to the devicetree
and no longer get passed an address to it.
TEST=abuild passes for all affected boards. All USB ports still work
on asus/p8x7x-series/v/p8z77-m.
Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81881
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index f2f02b3..8924dca 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -64,7 +64,7 @@
void pch_enable(struct device *dev);
extern const struct southbridge_usb_port mainboard_usb_ports[14];
-void early_usb_init(const struct southbridge_usb_port *portmap);
+void early_usb_init(void);
/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS 0x06