nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree
Transfer all USB responsibilities to southbridge/intel/bd82x6x,
using one set of USB port configuration supplied by mainboards
in the southbridge section of their devicetree.
For MRC raminit, export southbridge_fill_pei_data() as a hook for
southbridge code to implement. With new code via this hook, bd82x6x
fills pei_data based on this one set of USB port config.
For native raminit, early_usb_init() now goes directly to the devicetree
and no longer get passed an address to it.
TEST=abuild passes for all affected boards. All USB ports still work
on asus/p8x7x-series/v/p8z77-m.
Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81881
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index 6c21cf7..7bca0bb 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -8,8 +8,9 @@
#include <southbridge/intel/common/pmbase.h>
#include "pch.h"
+#include "chip.h"
-void early_usb_init(const struct southbridge_usb_port *portmap)
+void early_usb_init(void)
{
u32 reg32;
const u32 rcba_dump[8] = {
@@ -23,6 +24,9 @@
USBIR_TXRX_GAIN_DESKTOP6_LOW, USBIR_TXRX_GAIN_DESKTOP6_HIGH,
USBIR_TXRX_GAIN_DESKTOP7_LOW, USBIR_TXRX_GAIN_DESKTOP7_MED,
0x20000053, 0x2000055f, 0x20000f5f};
+ const struct device *dev = pcidev_on_root(0x1d, 0);
+ const struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
+ const struct southbridge_usb_port *portmap = config->usb_port_config;
int i;
/* Unlock registers. */