| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2010 Google Inc. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| |
| config NORTHBRIDGE_INTEL_SANDYBRIDGE |
| bool |
| select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE |
| select CPU_INTEL_MODEL_206AX |
| select HAVE_DEBUG_RAM_SETUP |
| select INTEL_GMA_ACPI |
| select RELOCATABLE_RAMSTAGE |
| |
| config NORTHBRIDGE_INTEL_IVYBRIDGE |
| bool |
| select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE |
| select CPU_INTEL_MODEL_306AX |
| select HAVE_DEBUG_RAM_SETUP |
| select INTEL_GMA_ACPI |
| select RELOCATABLE_RAMSTAGE |
| |
| if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE |
| |
| config VBOOT |
| select VBOOT_STARTS_IN_ROMSTAGE |
| |
| config USE_NATIVE_RAMINIT |
| bool "Use native raminit" |
| default y |
| help |
| Select if you want to use coreboot implementation of raminit rather than |
| System Agent/MRC.bin. You should answer Y. |
| |
| config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES |
| bool "Ignore vendor programmed fuses that limit max. DRAM frequency" |
| default n |
| depends on USE_NATIVE_RAMINIT |
| help |
| Ignore the mainboard's vendor programmed fuses that might limit the |
| maximum DRAM frequency. By selecting this option the fuses will be |
| ignored and the only limits on DRAM frequency are set by RAM's SPD and |
| hard fuses in southbridge's clockgen. |
| Disabled by default as it might causes system instability. |
| Handle with care! |
| |
| config CBFS_SIZE |
| hex |
| default 0x100000 |
| |
| config VGA_BIOS_ID |
| string |
| default "8086,0106" |
| |
| config CACHE_MRC_SIZE_KB |
| int |
| default 512 |
| |
| config SANDYBRIDGE_IVYBRIDGE_LVDS |
| def_bool n |
| select VGA |
| select MAINBOARD_HAS_NATIVE_VGA_INIT |
| |
| config IF_NATIVE_VGA_INIT |
| def_bool y |
| depends on MAINBOARD_DO_NATIVE_VGA_INIT |
| select VGA |
| select INTEL_EDID |
| select HAVE_LINEAR_FRAMEBUFFER |
| select HAVE_VGA_TEXT_FRAMEBUFFER |
| |
| config MRC_CACHE_SIZE |
| hex |
| depends on !CHROMEOS |
| default 0x10000 |
| |
| config BOOTBLOCK_NORTHBRIDGE_INIT |
| string |
| default "northbridge/intel/sandybridge/bootblock.c" |
| |
| config MMCONF_BASE_ADDRESS |
| hex |
| default 0xf8000000 if USE_NATIVE_RAMINIT |
| default 0xf0000000 |
| help |
| We can optimize the native case but the MRC blob requires it |
| to be at 0xf0000000. |
| |
| if USE_NATIVE_RAMINIT |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0xfefe0000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x20000 |
| |
| config DCACHE_RAM_MRC_VAR_SIZE |
| hex |
| default 0x0 |
| |
| endif # USE_NATIVE_RAMINIT |
| |
| if !USE_NATIVE_RAMINIT |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0xff7e0000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x1c000 |
| |
| config DCACHE_RAM_MRC_VAR_SIZE |
| hex |
| default 0x4000 |
| |
| config MRC_FILE |
| string "Intel System Agent path and filename" |
| default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin" |
| help |
| The path and filename of the file to use as System Agent |
| binary. |
| |
| endif # !USE_NATIVE_RAMINIT |
| |
| endif |