| chip soc/intel/cannonlake |
| |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route. i.e. If this route changes then the affected GPE |
| # offset bits also need to be changed. |
| # DW1 is used by: |
| # - GPP_C1 - PCIE_14_WLAN_WAKE_ODL |
| # - GPP_C21 - H1_PCH_INT_ODL |
| register "gpe0_dw0" = "PMC_GPP_A" |
| register "gpe0_dw1" = "PMC_GPP_C" |
| register "gpe0_dw2" = "PMC_GPP_D" |
| |
| # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| register "gen1_dec" = "0x00fc0801" |
| register "gen2_dec" = "0x000c0201" |
| # EC memory map range is 0x900-0x9ff |
| register "gen3_dec" = "0x00fc0901" |
| |
| # Intel Common SoC Config |
| #+-------------------+---------------------------+ |
| #| Field | Value | |
| #+-------------------+---------------------------+ |
| #| GSPI0 | cr50 TPM. Early init is | |
| #| | required to set up a BAR | |
| #| | for TPM communication | |
| #| | before memory is up | |
| #| I2C0 | Touchpad | |
| #| I2C1 | Touch screen | |
| #+-------------------+---------------------------+ |
| register "common_soc_config" = "{ |
| .gspi[0] = { |
| .speed_mhz = 1, |
| .early_init = 1, |
| }, |
| .i2c[0] = { |
| .speed = I2C_SPEED_FAST, |
| }, |
| .i2c[1] = { |
| .speed = I2C_SPEED_FAST, |
| }, |
| }" |
| |
| # FSP configuration |
| register "InternalGfx" = "1" |
| register "SkipExtGfxScan" = "1" |
| register "SataSalpSupport" = "1" |
| register "SataMode" = "Sata_AHCI" |
| register "SataPortsEnable[1]" = "1" |
| register "SataPortsDevSlp[1]" = "1" |
| register "satapwroptimize" = "1" |
| # Enable System Agent dynamic frequency |
| register "SaGv" = "SaGv_Enabled" |
| # Enable heci communication |
| register "HeciEnabled" = "1" |
| # Enable Speed Shift Technology support |
| register "speed_shift_enable" = "1" |
| # Enable S0ix |
| register "s0ix_enable" = "1" |
| |
| register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 |
| register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 |
| register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 |
| register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1 |
| register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # BT |
| register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN |
| register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera |
| register "usb2_ports[7]" = "USB2_PORT_EMPTY" |
| register "usb2_ports[8]" = "USB2_PORT_EMPTY" |
| register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT |
| |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 |
| register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 |
| register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1 |
| register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN |
| register "usb3_ports[5]" = "USB3_PORT_EMPTY" |
| |
| # Enable Root port 9(x4) for NVMe. |
| register "PcieRpEnable[8]" = "1" |
| # RP 9 uses CLK SRC 1 |
| register "PcieClkSrcUsage[1]" = "8" |
| # ClkReq-to-ClkSrc mapping for CLK SRC 1 |
| register "PcieClkSrcClkReq[1]" = "1" |
| |
| # GPIO for SD card detect |
| register "sdcard_cd_gpio" = "GPP_G5" |
| |
| # PCIe port 14 for M.2 E-key WLAN |
| register "PcieRpEnable[13]" = "1" |
| # RP 14 uses CLK SRC 3 |
| register "PcieClkSrcUsage[3]" = "13" |
| register "PcieClkSrcClkReq[3]" = "3" |
| |
| device cpu_cluster 0 on |
| device lapic 0 on end |
| end |
| |
| device domain 0 on |
| device pci 00.0 on end # Host Bridge |
| device pci 02.0 on end # Integrated Graphics Device |
| device pci 04.0 off end # SA Thermal device |
| device pci 05.0 off end # SA IPU |
| device pci 12.0 off end # Thermal Subsystem |
| device pci 12.5 off end # UFS SCS |
| device pci 12.6 off end # GSPI #2 |
| device pci 14.0 on |
| chip drivers/usb/acpi |
| register "desc" = ""Root Hub"" |
| register "type" = "UPC_TYPE_HUB" |
| device usb 0.0 on |
| chip drivers/usb/acpi |
| register "desc" = ""Left Type-C Port"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "group" = "ACPI_PLD_GROUP(1, 1)" |
| device usb 2.0 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Right Type-C Port 1"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "group" = "ACPI_PLD_GROUP(2, 1)" |
| device usb 2.1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Left Type-A Port"" |
| register "type" = "UPC_TYPE_A" |
| register "group" = "ACPI_PLD_GROUP(1, 2)" |
| device usb 2.2 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Right Type-A Port 1"" |
| register "type" = "UPC_TYPE_A" |
| register "group" = "ACPI_PLD_GROUP(2, 2)" |
| device usb 2.3 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Discrete bluetooth"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device usb 2.4 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""WWAN"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device usb 2.5 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Camera"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device usb 2.6 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Integrated CnVi bluetooth"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device usb 2.9 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Left Type-C Port"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "group" = "ACPI_PLD_GROUP(1, 1)" |
| device usb 3.0 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Right Type-C Port 1"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "group" = "ACPI_PLD_GROUP(2, 1)" |
| device usb 3.1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Left Type-A Port"" |
| register "type" = "UPC_TYPE_USB3_A" |
| register "group" = "ACPI_PLD_GROUP(1, 2)" |
| device usb 3.2 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Right Type-A Port 1"" |
| register "type" = "UPC_TYPE_USB3_A" |
| register "group" = "ACPI_PLD_GROUP(2, 2)" |
| device usb 3.3 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""WWAN"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device usb 3.4 on end |
| end |
| end |
| end |
| end # USB xHCI |
| device pci 14.1 off end # USB xDCI (OTG) |
| chip drivers/intel/wifi |
| register "wake" = "GPE0_PME_B0" |
| device pci 14.3 on end # CNVi wifi |
| end |
| device pci 14.5 on end # SDCard |
| device pci 15.0 on |
| chip drivers/i2c/generic |
| register "hid" = ""ELAN0000"" |
| register "desc" = ""ELAN Touchpad"" |
| register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)" |
| device i2c 15 on end |
| end |
| end # I2C #0 |
| device pci 15.1 on |
| chip drivers/i2c/generic |
| register "hid" = ""ELAN0001"" |
| register "desc" = ""ELAN Touchscreen"" |
| register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" |
| register "probed" = "1" |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" |
| register "reset_delay_ms" = "100" |
| register "reset_off_delay_ms" = "5" |
| register "has_power_resource" = "1" |
| register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" |
| register "stop_off_delay_ms" = "5" |
| device i2c 49 on end |
| end |
| end # I2C #1 |
| device pci 15.2 on end # I2C #2 |
| device pci 15.3 on end # I2C #3 |
| device pci 16.0 on end # Management Engine Interface 1 |
| device pci 16.1 off end # Management Engine Interface 2 |
| device pci 16.2 off end # Management Engine IDE-R |
| device pci 16.3 off end # Management Engine KT Redirection |
| device pci 16.4 off end # Management Engine Interface 3 |
| device pci 16.5 off end # Management Engine Interface 4 |
| device pci 17.0 on end # SATA |
| device pci 19.0 on end # I2C #4 |
| device pci 19.1 off end # I2C #5 |
| device pci 19.2 off end # UART #2 |
| device pci 1a.0 off end # eMMC |
| device pci 1c.0 off end # PCI Express Port 1 (USB) |
| device pci 1c.1 off end # PCI Express Port 2 (USB) |
| device pci 1c.2 off end # PCI Express Port 3 (USB) |
| device pci 1c.3 off end # PCI Express Port 4 (USB) |
| device pci 1c.4 off end # PCI Express Port 5 (USB) |
| device pci 1c.5 off end # PCI Express Port 6 |
| device pci 1c.6 off end # PCI Express Port 7 |
| device pci 1c.7 off end # PCI Express Port 8 |
| device pci 1d.0 on end # PCI Express Port 9 (X4 NVME) |
| device pci 1d.1 off end # PCI Express Port 10 |
| device pci 1d.2 off end # PCI Express Port 11 |
| device pci 1d.3 off end # PCI Express Port 12 |
| device pci 1d.4 off end # PCI Express port 13 |
| device pci 1d.5 on |
| chip drivers/intel/wifi |
| register "wake" = "GPE0_DW1_01" |
| device pci 00.0 on end |
| end |
| end # PCI Express Port 14 (x4) |
| device pci 1e.0 on end # UART #0 |
| device pci 1e.1 off end # UART #1 |
| device pci 1e.2 on |
| chip drivers/spi/acpi |
| register "hid" = "ACPI_DT_NAMESPACE_HID" |
| register "compat_string" = ""google,cr50"" |
| register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" |
| device spi 0 on end |
| end |
| end # GSPI #0 |
| device pci 1e.3 off end # GSPI #1 |
| device pci 1f.0 on |
| chip ec/google/chromeec |
| device pnp 0c09.0 on end |
| end |
| end # eSPI Interface |
| device pci 1f.1 on end # P2SB |
| device pci 1f.2 on end # Power Management Controller |
| device pci 1f.3 off end # Intel HDA |
| device pci 1f.4 on end # SMBus |
| device pci 1f.5 on end # PCH SPI |
| device pci 1f.6 off end # GbE |
| end |
| end |