| chip soc/intel/alderlake |
| register "domain_vr_config[VR_DOMAIN_IA]" = "{ |
| .enable_fast_vmode = 1, |
| }" |
| |
| register "sagv" = "SaGv_Enabled" |
| |
| register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 |
| register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 |
| register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5 |
| register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6 |
| register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 |
| register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 |
| |
| register "usb3_ports[0]" = "{ |
| .enable = 1, |
| .ocpin = OC_SKIP, |
| .tx_de_emp = 0x2B, |
| .tx_downscale_amp = 0x00, |
| }" # Type-A port A2 |
| register "usb3_ports[1]" = "{ |
| .enable = 1, |
| .ocpin = OC_SKIP, |
| .tx_de_emp = 0x2B, |
| .tx_downscale_amp = 0x00, |
| }" # Type-A port A3 |
| |
| register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable Type-A port |
| register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable Type-A port |
| |
| register "serial_io_i2c_mode" = "{ |
| [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| }" |
| |
| register "serial_io_gspi_mode" = "{ |
| [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, |
| [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |
| }" |
| |
| register "serial_io_uart_mode" = "{ |
| [PchSerialIoIndexUART0] = PchSerialIoPci, |
| [PchSerialIoIndexUART1] = PchSerialIoSkipInit, |
| [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| }" |
| |
| register "ddi_ports_config" = "{ |
| [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, |
| [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, |
| }" |
| |
| # Intel Common SoC Config |
| #+-------------------+---------------------------+ |
| #| Field | Value | |
| #+-------------------+---------------------------+ |
| #| I2C0 | Scaler | |
| #| I2C1 | cr50 TPM. Early init is | |
| #| | required to set up a BAR | |
| #| | for TPM communication | |
| #| I2C2 | HDMI_A | |
| #| I2C3 | Touchscreen | |
| #| I2C5 | TPU | |
| #+-------------------+---------------------------+ |
| register "common_soc_config" = "{ |
| .i2c[0] = { |
| .speed = I2C_SPEED_FAST, |
| }, |
| .i2c[1] = { |
| .early_init = 1, |
| .speed = I2C_SPEED_FAST, |
| .rise_time_ns = 600, |
| .fall_time_ns = 400, |
| .data_hold_time_ns = 50, |
| }, |
| .i2c[2] = { |
| .speed = I2C_SPEED_FAST, |
| }, |
| .i2c[3] = { |
| .speed = I2C_SPEED_FAST, |
| .rise_time_ns = 650, |
| .fall_time_ns = 400, |
| .data_hold_time_ns = 50, |
| }, |
| .i2c[5] = { |
| .speed = I2C_SPEED_FAST, |
| }, |
| }" |
| |
| device domain 0 on |
| device ref dtt on |
| chip drivers/intel/dptf |
| ## sensor information |
| register "options.tsr[0].desc" = ""DRAM"" |
| register "options.tsr[1].desc" = ""Charger"" |
| |
| # TODO: below values are initial reference values only |
| ## Active Policy |
| register "policies.active" = "{ |
| [0] = { |
| .target = DPTF_CPU, |
| .thresholds = { |
| TEMP_PCT(85, 90), |
| TEMP_PCT(80, 80), |
| TEMP_PCT(75, 70), |
| } |
| } |
| }" |
| |
| ## Passive Policy |
| register "policies.passive" = "{ |
| [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), |
| [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), |
| [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), |
| }" |
| |
| ## Critical Policy |
| register "policies.critical" = "{ |
| [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), |
| [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), |
| [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), |
| }" |
| |
| register "controls.power_limits" = "{ |
| .pl1 = { |
| .min_power = 3000, |
| .max_power = 15000, |
| .time_window_min = 28 * MSECS_PER_SEC, |
| .time_window_max = 32 * MSECS_PER_SEC, |
| .granularity = 200, |
| }, |
| .pl2 = { |
| .min_power = 55000, |
| .max_power = 55000, |
| .time_window_min = 28 * MSECS_PER_SEC, |
| .time_window_max = 32 * MSECS_PER_SEC, |
| .granularity = 1000, |
| } |
| }" |
| |
| ## Charger Performance Control (Control, mA) |
| register "controls.charger_perf" = "{ |
| [0] = { 255, 1700 }, |
| [1] = { 24, 1500 }, |
| [2] = { 16, 1000 }, |
| [3] = { 8, 500 } |
| }" |
| |
| ## Fan Performance Control (Percent, Speed, Noise, Power) |
| register "controls.fan_perf" = "{ |
| [0] = { 90, 6700, 220, 2200, }, |
| [1] = { 80, 5800, 180, 1800, }, |
| [2] = { 70, 5000, 145, 1450, }, |
| [3] = { 60, 4900, 115, 1150, }, |
| [4] = { 50, 3838, 90, 900, }, |
| [5] = { 40, 2904, 55, 550, }, |
| [6] = { 30, 2337, 30, 300, }, |
| [7] = { 20, 1608, 15, 150, }, |
| [8] = { 10, 800, 10, 100, }, |
| [9] = { 0, 0, 0, 50, } |
| }" |
| |
| ## Fan options |
| register "options.fan.fine_grained_control" = "1" |
| register "options.fan.step_size" = "2" |
| |
| device generic 0 alias dptf_policy on end |
| end |
| end |
| device ref pcie4_0 on |
| # Enable CPU PCIE RP 1 using CLK 0 |
| register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| .clk_req = 0, |
| .clk_src = 0, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| end |
| device ref cnvi_wifi on |
| chip drivers/wifi/generic |
| register "wake" = "GPE0_PME_B0" |
| device generic 0 on end |
| end |
| end |
| device ref i2c0 on end # Scaler |
| device ref i2c1 on |
| chip drivers/i2c/tpm |
| register "hid" = ""GOOG0005"" |
| register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" |
| device i2c 50 on end |
| end |
| end #TPM |
| device ref i2c2 on end # HDMI_A |
| device ref i2c3 on |
| chip drivers/i2c/hid |
| register "generic.hid" = ""ILTK0001"" |
| register "generic.desc" = ""ILITEK Touchscreen"" |
| register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" |
| register "generic.detect" = "1" |
| register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" |
| register "generic.reset_delay_ms" = "200" |
| register "generic.enable_delay_ms" = "12" |
| register "generic.has_power_resource" = "1" |
| register "hid_desc_reg_offset" = "0x01" |
| device i2c 41 on end |
| end |
| end # Touch screen |
| device ref i2c5 on end # TPU |
| device ref pcie_rp6 on |
| # Enable PCIE 6 using clk 3 |
| register "pch_pcie_rp[PCH_RP(6)]" = "{ |
| .clk_src = 3, |
| .clk_req = 3, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| end #TPU0 |
| device ref pcie_rp7 on |
| # Enable PCIE 7 using clk 6 |
| register "pch_pcie_rp[PCH_RP(7)]" = "{ |
| .clk_src = 6, |
| .clk_req = 6, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| chip drivers/net |
| register "customized_leds" = "0x05af" |
| register "wake" = "GPE0_DW0_07" # GPP_A7 |
| register "device_index" = "0" |
| register "enable_aspm_l1_2" = "1" |
| device pci 00.0 on end |
| end |
| end # RTL8111H Ethernet NIC |
| device ref pcie_rp8 on |
| # Enable PCIE 8 using clk 4 |
| register "pch_pcie_rp[PCH_RP(8)]" = "{ |
| .clk_src = 4, |
| .clk_req = 4, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| end #TPU1 |
| device ref uart0 on end |
| device ref uart1 on end |
| device ref gspi0 off end |
| device ref gspi1 off end |
| device ref pch_espi on |
| chip ec/google/chromeec |
| use conn0 as mux_conn[0] |
| device pnp 0c09.0 on end |
| end |
| end |
| device ref pmc hidden |
| chip drivers/intel/pmc_mux |
| device generic 0 on |
| chip drivers/intel/pmc_mux/conn |
| use usb2_port1 as usb2_port |
| use tcss_usb3_port1 as usb3_port |
| device generic 0 alias conn0 on end |
| end |
| end |
| end |
| end |
| device ref tcss_xhci on |
| chip drivers/usb/acpi |
| device ref tcss_root_hub on |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-C Port C0 (MLB)"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 0))" |
| device ref tcss_usb3_port1 on end |
| end |
| end |
| end |
| end |
| device ref xhci on |
| chip drivers/usb/acpi |
| device ref xhci_root_hub on |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-C Port C0 (MLB)"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 0))" |
| device ref usb2_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Port A3 (MLB)"" |
| register "type" = "UPC_TYPE_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(0, 1))" |
| device ref usb2_port3 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Port A2 (MLB)"" |
| register "type" = "UPC_TYPE_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(0, 0))" |
| device ref usb2_port4 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Bluetooth"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| register "reset_gpio" = |
| "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" |
| device ref usb2_port10 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-A Port A2 (MLB)"" |
| register "type" = "UPC_TYPE_USB3_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(0, 0))" |
| device ref usb3_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-A Port A3 (MLB)"" |
| register "type" = "UPC_TYPE_USB3_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(0, 1))" |
| device ref usb3_port2 on end |
| end |
| end |
| end |
| end |
| end |
| |
| end |