| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright 2018 Google LLC |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <arch/acpi.h> |
| #include <baseboard/variants.h> |
| #include <soc/ramstage.h> |
| #include <variant/gpio.h> |
| #include <vendorcode/google/chromeos/chromeos.h> |
| |
| void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| { |
| const struct pad_config *gpio_table; |
| size_t num_gpios; |
| |
| gpio_table = variant_base_gpio_table(&num_gpios); |
| gpio_configure_pads(gpio_table, num_gpios); |
| } |
| |
| static void mainboard_enable(struct device *dev) |
| { |
| dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; |
| } |
| |
| struct chip_operations mainboard_ops = { |
| .enable_dev = mainboard_enable, |
| }; |