| /* SPDX-License-Identifier: GPL-2.0-only */ |
| /* This file is part of the coreboot project. */ |
| |
| #include <arch/acpigen.h> |
| #include <arch/ioapic.h> |
| #include <arch/smp/mpspec.h> |
| #include <cbmem.h> |
| #include <cf9_reset.h> |
| #include <console/console.h> |
| #include <cpu/x86/smm.h> |
| #include <device/pci.h> |
| #include <intelblocks/acpi.h> |
| #include <soc/iomap.h> |
| #include <soc/nvs.h> |
| #include <soc/pm.h> |
| |
| #include "chip.h" |
| |
| #define SCI_INT_NUM 9 |
| |
| unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, |
| struct acpi_rsdp *rsdp) |
| { |
| current = acpi_write_hpet(device, current, rsdp); |
| current = (ALIGN(current, 16)); |
| printk(BIOS_DEBUG, "current = %lx\n", current); |
| return current; |
| } |
| |
| unsigned long acpi_fill_mcfg(unsigned long current) |
| { |
| current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); |
| return current; |
| } |
| |
| void southbridge_inject_dsdt(const struct device *device) |
| { |
| global_nvs_t *gnvs; |
| |
| gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| if (!gnvs) { |
| gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, 0x2000); |
| if (gnvs) |
| memset(gnvs, 0, sizeof(*gnvs)); |
| } |
| |
| if (gnvs) { |
| acpi_create_gnvs(gnvs); |
| /* TODO: tell SMI about it, if HAVE_SMI_HANDLER */ |
| // smm_setup_structures(gnvs, NULL, NULL); |
| |
| /* Add it to DSDT. */ |
| printk(BIOS_SPEW, "%s injecting NVSA with 0x%x\n", __FILE__, (uint32_t)gnvs); |
| acpigen_write_scope("\\"); |
| acpigen_write_name_dword("NVSA", (uint32_t)gnvs); |
| acpigen_pop_len(); |
| } |
| } |
| |
| void acpi_create_gnvs(struct global_nvs_t *gnvs) |
| { |
| config_t *config = config_of_soc(); |
| (void) config; |
| /* not implemented yet */ |
| } |
| |
| static unsigned long acpi_madt_irq_overrides(unsigned long current) |
| { |
| int sci = SCI_INT_NUM; |
| uint16_t flags = MP_IRQ_TRIGGER_LEVEL; |
| |
| /* INT_SRC_OVR */ |
| current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); |
| |
| flags |= soc_madt_sci_irq_polarity(sci); |
| |
| /* SCI */ |
| current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); |
| |
| return current; |
| } |
| |
| unsigned long acpi_fill_madt(unsigned long current) |
| { |
| /* Local APICs */ |
| current = acpi_create_madt_lapics(current); |
| |
| /* IOAPIC */ |
| current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0); |
| |
| return acpi_madt_irq_overrides(current); |
| } |
| |
| int soc_madt_sci_irq_polarity(int sci) |
| { |
| if (sci >= 20) |
| return MP_IRQ_POLARITY_LOW; |
| else |
| return MP_IRQ_POLARITY_HIGH; |
| } |
| |
| void acpi_fill_fadt(acpi_fadt_t *fadt) |
| { |
| |
| const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| |
| fadt->header.revision = get_acpi_table_revision(FADT); |
| fadt->sci_int = SCI_INT_NUM; |
| |
| fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| fadt->pm1b_evt_blk = 0x0; |
| fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| fadt->pm1b_cnt_blk = 0x0; |
| |
| fadt->gpe0_blk = pmbase + GPE0_STS(0); |
| |
| fadt->pm1_evt_len = 4; |
| fadt->pm1_cnt_len = 2; |
| |
| /* GPE0 STS/EN pairs each 32 bits wide. */ |
| fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); |
| |
| fadt->flush_size = 0x400; /* twice of cache size */ |
| fadt->flush_stride = 0x10; /* Cache line width */ |
| fadt->duty_offset = 1; |
| fadt->day_alrm = 0xd; |
| |
| fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_C2_MP_SUPPORTED | |
| ACPI_FADT_RESET_REGISTER | ACPI_FADT_PLATFORM_CLOCK; |
| |
| fadt->reset_reg.space_id = 1; |
| fadt->reset_reg.bit_width = 8; |
| fadt->reset_reg.addrl = RST_CNT; |
| fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| fadt->reset_value = RST_CPU | SYS_RST; |
| |
| fadt->x_pm1a_evt_blk.space_id = 1; |
| fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
| fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; |
| |
| fadt->x_pm1b_evt_blk.space_id = 1; |
| |
| fadt->x_pm1a_cnt_blk.space_id = 1; |
| fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
| fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; |
| |
| fadt->x_pm1b_cnt_blk.space_id = 1; |
| |
| fadt->x_gpe1_blk.space_id = 1; |
| |
| if (CONFIG(HAVE_SMI_HANDLER)) { |
| fadt->smi_cmd = APM_CNT; |
| fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| fadt->s4bios_req = 0; |
| fadt->pstate_cnt = 0; |
| fadt->cst_cnt = 0; |
| } else { |
| fadt->smi_cmd = 0; |
| fadt->acpi_enable = 0; |
| fadt->acpi_disable = 0; |
| fadt->s4bios_req = 0; |
| fadt->pstate_cnt = 0; |
| fadt->cst_cnt = 0; |
| } |
| |
| /* General-Purpose Event Registers */ |
| fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ |
| fadt->x_gpe0_blk.bit_offset = 0; |
| fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; |
| fadt->x_gpe0_blk.addrh = 0; |
| |
| fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| fadt->x_gpe1_blk.bit_width = 0; |
| fadt->x_gpe1_blk.bit_offset = 0; |
| fadt->x_gpe1_blk.access_size = 0; |
| fadt->x_gpe1_blk.addrl = 0; |
| fadt->x_gpe1_blk.addrh = 0; |
| } |