| /* SPDX-License-Identifier: GPL-2.0-only */ |
| /* This file is part of the coreboot project. */ |
| |
| #include <arch/acpi.h> |
| |
| DefinitionBlock( |
| "dsdt.aml", |
| "DSDT", |
| 0x05, // DSDT revision: ACPI v5.0 |
| "COREv4", // OEM id |
| "COREBOOT", // OEM table id |
| 0x20110725 // OEM revision |
| ){ |
| //Platform |
| #include <soc/intel/skylake/acpi/platform.asl> |
| |
| // global NVS and variables |
| #include <soc/intel/skylake/acpi/globalnvs.asl> |
| |
| // CPU |
| #include <cpu/intel/common/acpi/cpu.asl> |
| |
| Scope (\_SB) { |
| Device (PCI0) |
| { |
| #include <soc/intel/skylake/acpi/systemagent.asl> |
| #include <soc/intel/skylake/acpi/pch.asl> |
| } |
| |
| } |
| |
| #include <southbridge/intel/common/acpi/sleepstates.asl> |
| |
| #include "acpi/mainboard.asl" |
| } |