| config SOC_INTEL_APOLLOLAKE |
| bool |
| help |
| Intel Apollolake support |
| |
| if SOC_INTEL_APOLLOLAKE |
| |
| config CPU_SPECIFIC_OPTIONS |
| def_bool y |
| select ARCH_BOOTBLOCK_X86_32 |
| select ARCH_RAMSTAGE_X86_32 |
| select ARCH_ROMSTAGE_X86_32 |
| select ARCH_VERSTAGE_X86_32 |
| # CPU specific options |
| select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| select IOAPIC |
| select SMP |
| select SSE2 |
| select SUPPORT_CPU_UCODE_IN_CBFS |
| # Misc options |
| select C_ENVIRONMENT_BOOTBLOCK |
| select COLLECT_TIMESTAMPS |
| select HAVE_INTEL_FIRMWARE |
| select MMCONF_SUPPORT |
| select MMCONF_SUPPORT_DEFAULT |
| select PARALLEL_MP |
| select PCIEXP_ASPM |
| select PCIEXP_COMMON_CLOCK |
| select PCIEXP_CLK_PM |
| select PCIEXP_L1_SUB_STATE |
| select REG_SCRIPT |
| select RELOCATABLE_RAMSTAGE # Build fails if this is not selected |
| select SOC_INTEL_COMMON |
| select UDELAY_TSC |
| |
| config MMCONF_BASE_ADDRESS |
| hex "PCI MMIO Base Address" |
| default 0xe0000000 |
| |
| config IOSF_BASE_ADDRESS |
| hex "MMIO Base Address of sideband bus" |
| default 0xd0000000 |
| |
| config DCACHE_RAM_BASE |
| hex "Base address of cache-as-RAM" |
| default 0xfef00000 |
| |
| config DCACHE_RAM_SIZE |
| hex "Length in bytes of cache-as-RAM" |
| default 0x80000 |
| help |
| The size of the cache-as-ram region required during bootblock |
| and/or romstage. |
| |
| config DCACHE_BSP_STACK_SIZE |
| hex |
| default 0x4000 |
| help |
| The amount of anticipated stack usage in CAR by bootblock and |
| other stages. |
| |
| config CPU_ADDR_BITS |
| int |
| default 36 |
| |
| endif |