/* SPDX-License-Identifier: GPL-2.0-only */ | |
#ifndef AMD_STONEYRIDGE_AOAC_DEFS_H | |
#define AMD_STONEYRIDGE_AOAC_DEFS_H | |
/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ | |
#define FCH_AOAC_DEV_CLK_GEN 0 | |
#define FCH_AOAC_DEV_I2C0 5 | |
#define FCH_AOAC_DEV_I2C1 6 | |
#define FCH_AOAC_DEV_I2C2 7 | |
#define FCH_AOAC_DEV_I2C3 8 | |
#define FCH_AOAC_DEV_UART0 11 | |
#define FCH_AOAC_DEV_UART1 12 | |
#define FCH_AOAC_DEV_AMBA 17 | |
#define FCH_AOAC_DEV_USB2 18 | |
#define FCH_AOAC_DEV_USB3 23 | |
#endif /* AMD_STONEYRIDGE_AOAC_DEFS_H */ |