mb/clevo/kbl-u: Add Clevo N130WU/N131WU
Working:
- TianoCore
- NVMe, SATA3
- USB2, USB3
- Thunderbolt
- Graphics (GOP and libgfxinit)
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
- ACPI S3
WIP:
- Documentation
Not working:
- EC ACPI (e.g. Fn keys, battery and power information)
Boots Arch Linux (Linux 5.8.12) successfully.
Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
diff --git a/Documentation/mainboard/clevo/n130wu/index.md b/Documentation/mainboard/clevo/n130wu/index.md
new file mode 100644
index 0000000..3267561
--- /dev/null
+++ b/Documentation/mainboard/clevo/n130wu/index.md
@@ -0,0 +1,47 @@
+# Clevo N130WU
+
+## Hardware
+### Technology
+```eval_rst
++------------------+--------------------------------+
+| CPU | Intel i7-8550U |
++------------------+--------------------------------+
+| PCH | Intel Sunrise Point LP |
++------------------+--------------------------------+
+| EC / Super IO | ITE IT8587E |
++------------------+--------------------------------+
+| Coprocessor | Intel ME |
++------------------+--------------------------------+
+```
+
+### Flash chip
+```eval_rst
++---------------------+-----------------+
+| Type | Value |
++=====================+=================+
+| Model | GD25Q64B |
++---------------------+-----------------+
+| Socketed flash | no |
++---------------------+-----------------+
+| Size | 8 MiB |
++---------------------+-----------------+
+| In circuit flashing | Yes |
++---------------------+-----------------+
+| Package | SOIC-8 |
++---------------------+-----------------+
+| Write protection | No |
++---------------------+-----------------+
+| Dual BIOS feature | No |
++---------------------+-----------------+
+| Internal flashing | Yes |
++---------------------+-----------------+
+```
+
+## Board status
+### Working
+### Not Working
+### Work in progress
+### Untested
+
+## Also known as
+* TUXEDO InfinityBook Pro 13 v3
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 4a1f74b..d6aed22 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -26,6 +26,10 @@
- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
+## Clevo
+
+- [N130WU / N131WU](clevo/n130wu/index.md)
+
## Dell
- [OptiPlex 9010 SFF](dell/optiplex_9010.md)
diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig
new file mode 100644
index 0000000..ed0600a
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/Kconfig
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_CLEVO_N130WU
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_8192
+ select EC_ACPI
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+# select HAVE_CMOS_DEFAULT
+# select HAVE_SMI_HANDLER
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_LPC_TPM
+ select MAINBOARD_HAS_TPM2
+ select NO_UART_ON_SUPERIO
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SOC_INTEL_KABYLAKE
+ select SPD_READ_BY_WORD
+ select SYSTEM_TYPE_LAPTOP
+
+config VBOOT
+ select VBOOT_NO_BOARD_SUPPORT
+ select GBB_FLAG_DISABLE_LID_SHUTDOWN
+ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+ select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+ select GBB_FLAG_DISABLE_FWMP
+
+config MAINBOARD_DIR
+ string
+ default "clevo/kbl-u"
+
+config VARIANT_DIR
+ string
+ default "n13xwu" if BOARD_CLEVO_N130WU
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "N130WU" if BOARD_CLEVO_N130WU
+
+config CBFS_SIZE
+ hex
+ default 0x600000 if BOARD_CLEVO_N130WU
+
+config DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config FMDFILE
+ string
+ default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/fmds/vboot-ro.fmd" if VBOOT && !VBOOT_SLOTS_RW_A
+ # TODO
+# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roa.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB
+# default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/fmds/vboot-roab.fmd" if VBOOT_SLOTS_RW_AB
+
+config MAX_CPUS
+ int
+ default 8
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config VGA_BIOS_ID
+ string
+ default "8086,5917" if BOARD_CLEVO_N130WU
+
+config PXE_ROM_ID
+ string
+ default "10ec,8168"
+
+config UART_FOR_CONSOLE
+ int
+ default 2
+
+config POST_DEVICE
+ bool
+ default n
+
+config CONSOLE_POST
+ bool
+ default y
+
+config LINEAR_FRAMEBUFFER_MAX_WIDTH
+ int
+ default 1920
+
+config LINEAR_FRAMEBUFFER_MAX_HEIGHT
+ int
+ default 1080
+
+endif
diff --git a/src/mainboard/clevo/kbl-u/Kconfig.name b/src/mainboard/clevo/kbl-u/Kconfig.name
new file mode 100644
index 0000000..5a6f699c
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/Kconfig.name
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+comment "Kaby Lake U"
+
+config BOARD_CLEVO_N130WU
+ bool "N130WU / N131WU"
diff --git a/src/mainboard/clevo/kbl-u/Makefile.inc b/src/mainboard/clevo/kbl-u/Makefile.inc
new file mode 100644
index 0000000..b424d4d
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/Makefile.inc
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
diff --git a/src/mainboard/clevo/kbl-u/acpi/ec.asl b/src/mainboard/clevo/kbl-u/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/acpi/ec.asl
diff --git a/src/mainboard/clevo/kbl-u/acpi/superio.asl b/src/mainboard/clevo/kbl-u/acpi/superio.asl
new file mode 100644
index 0000000..55b1db5
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/clevo/kbl-u/board_info.txt b/src/mainboard/clevo/kbl-u/board_info.txt
new file mode 100644
index 0000000..97514fc
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/board_info.txt
@@ -0,0 +1,7 @@
+Vendor name: Clevo
+Category: laptop
+Release year: 2018
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/clevo/kbl-u/bootblock.c b/src/mainboard/clevo/kbl-u/bootblock.c
new file mode 100644
index 0000000..067c9ec
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <mainboard/gpio.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ mainboard_configure_gpios();
+}
diff --git a/src/mainboard/clevo/kbl-u/dsdt.asl b/src/mainboard/clevo/kbl-u/dsdt.asl
new file mode 100644
index 0000000..21acf37
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/dsdt.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0) {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/clevo/kbl-u/include/mainboard/gpio.h b/src/mainboard/clevo/kbl-u/include/mainboard/gpio.h
new file mode 100644
index 0000000..ef2a21c
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/include/mainboard/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/clevo/kbl-u/ramstage.c b/src/mainboard/clevo/kbl-u/ramstage.c
new file mode 100644
index 0000000..b5d6786
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/ramstage.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/ramstage.h>
+
+/*
+ * TODO:
+ * - Add kill switches for WLAN, BT, LTE, CCD
+ * - Add support for WoL (LAN, WLAN)
+ * - Make M.2 port configurable (SATA <> PCIe)
+ * - Make SATA DevSlp configurable
+ * - Make TBT port configurable (TBT <> DisplayPort)
+ */
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ mainboard_configure_gpios();
+}
diff --git a/src/mainboard/clevo/kbl-u/romstage.c b/src/mainboard/clevo/kbl-u/romstage.c
new file mode 100644
index 0000000..1399d33
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/romstage.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ const u16 RcompResistor[3] = {121, 81, 100};
+ memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ const u16 RcompTarget[5] = {100, 40, 20, 20, 26};
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ struct spd_block blk = {
+ .addr_map = {0x50, 0x52},
+ };
+
+ mem_cfg = &mupd->FspmConfig;
+
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ mem_cfg->DqPinsInterleaved = TRUE;
+ mem_cfg->MemorySpdDataLen = blk.len;
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+}
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt b/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt
new file mode 100644
index 0000000..30f8ce6
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/board_info.txt
@@ -0,0 +1 @@
+Board name: N130WU / N131WU
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt
new file mode 100644
index 0000000..f88aef4
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/data.vbt
Binary files differ
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
new file mode 100644
index 0000000..55c5a69
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
@@ -0,0 +1,166 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+ register "gpu_pp_up_delay_ms" = "200" # T3
+ register "gpu_pp_down_delay_ms" = " 0" # T10
+ register "gpu_pp_cycle_delay_ms" = "500" # T12
+ register "gpu_pp_backlight_on_delay_ms" = " 50" # T7
+ register "gpu_pp_backlight_off_delay_ms" = " 0" # T9
+
+ register "gpu_pch_backlight_pwm_hz" = "200"
+
+ # IGD Displays
+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+ # FSP Configuration
+ register "SkipExtGfxScan" = "1"
+ register "SaGv" = "SaGv_Enabled"
+ register "eist_enable" = "1"
+
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 20,
+ .tdp_pl2_override = 30,
+ }"
+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ }"
+
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
+ }"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ subsystemid 0x1558 0x1313 inherit
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on end # SA thermal subsystem
+ device pci 05.0 off end # Imaging Unit
+ device pci 08.0 on end # Gaussian Mixture Model
+ device pci 13.0 off end # Sensor Hub
+ device pci 14.0 on # USB xHCI
+ register "SsicPortEnable" = "0"
+ # USB2
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right
+ register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right
+ register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
+ register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
+ register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A, left
+ register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right
+ # USB3
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left
+ end
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 14.3 off end # Camera
+ device pci 15.0 off end # I2C0
+ device pci 15.1 off end # I2C1
+ device pci 15.2 off end # I2C2
+ device pci 15.3 off end # I2C3
+ device pci 16.0 on # Management Engine Interface 1
+ register "HeciEnabled" = "1"
+ end
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 on # SATA
+ register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
+ register "SataSalpSupport" = "0"
+ # Ports
+ register "SataPortsEnable[0]" = "1"
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[2]" = "1"
+ end
+ device pci 19.0 on end # UART 2
+ device pci 19.1 off end # I2C5
+ device pci 19.2 off end # I2C4
+ device pci 1c.0 on # PCI Express Port 1
+ device pci 00.0 on end # x4 TBT
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "4"
+ register "PcieRpClkSrcNumber[0]" = "4"
+ register "PcieRpHotPlug[0]" = "1"
+ register "PcieRpLtrEnable[0]" = "1"
+ smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X"
+ end
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 on # PCI Express Port 5
+ device pci 00.0 on end # x1 LAN
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "3"
+ register "PcieRpClkSrcNumber[4]" = "3"
+ register "PcieRpLtrEnable[4]" = "1"
+ end
+ device pci 1c.5 on # PCI Express Port 6
+ device pci 00.0 on end # x1 WLAN
+ register "PcieRpEnable[5]" = "1"
+ register "PcieRpClkReqSupport[5]" = "1"
+ register "PcieRpClkReqNumber[5]" = "2"
+ register "PcieRpClkSrcNumber[5]" = "2"
+ register "PcieRpLtrEnable[5]" = "1"
+ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
+ end
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 on # PCI Express Port 9
+ device pci 00.0 on end # x4 M.2/M (J_SSD1)
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "5"
+ register "PcieRpClkSrcNumber[8]" = "5"
+ register "PcieRpLtrEnable[8]" = "1"
+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
+ end
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 off end # UART 0
+ device pci 1e.1 off end # UART 1
+ device pci 1e.2 off end # GSPI 0
+ device pci 1e.3 off end # GSPI 1
+ device pci 1e.4 off end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDXC
+ device pci 1f.0 on # LPC Interface
+ register "gen1_dec" = "0x000c0681"
+ register "gen2_dec" = "0x000c1641"
+ register "gen3_dec" = "0x000c0081"
+ register "gen4_dec" = "0x00040069"
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end
+ device pci 1f.1 hidden end # P2SB
+ device pci 1f.2 on # Power Management Controller
+ register "gpe0_dw0" = "GPP_C"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+ end
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ device pci 1f.7 off end # Trace Hub
+ end
+end
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd b/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd
new file mode 100644
index 0000000..f53cdf4
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/fmds/vboot-ro.fmd
@@ -0,0 +1,32 @@
+FLASH 8M {
+ SI_ALL@0x0 0x200000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x1ff000
+ }
+ SI_BIOS@0x200000 0x600000 {
+ MISC_RW@0x0 0x2d000 {
+ UNIFIED_MRC_CACHE@0x0 0x21000 {
+ RECOVERY_MRC_CACHE@0x0 0x10000
+ RW_MRC_CACHE@0x10000 0x10000
+ RW_VAR_MRC_CACHE@0x20000 0x1000
+ }
+ RW_SHARED@0x21000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD(PRESERVE)@0x25000 0x2000
+ RW_NVRAM(PRESERVE)@0x27000 0x5000
+ FPF_STATUS@0x2c000 0x1000
+ }
+ WP_RO@0x2d000 0x5d3000 {
+ FMAP@0x0 0x800
+ RO_VPD(PRESERVE)@0x800 0x4000
+ RO_SECTION@0x4800 0x5ce800 {
+ RO_FRID@0x0 0x40
+ RO_FRID_PAD@0x40 0x7c0
+ GBB@0x800 0x40000
+ COREBOOT(CBFS)@0x40800 0x58e000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads b/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads
new file mode 100644
index 0000000..38abb7a
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gma-mainboard.ads
@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (eDP,
+ DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c
new file mode 100644
index 0000000..e7aadcc
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c
@@ -0,0 +1,503 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+ // RCIN#
+ _PAD_CFG_STRUCT(GPP_A0, 0x44000502, 0x0),
+
+ // LAD0
+ _PAD_CFG_STRUCT(GPP_A1, 0x44000402, 0x0),
+
+ // LAD1
+ _PAD_CFG_STRUCT(GPP_A2, 0x44000402, 0x0),
+
+ // LAD2
+ _PAD_CFG_STRUCT(GPP_A3, 0x44000402, 0x0),
+
+ // LAD3
+ _PAD_CFG_STRUCT(GPP_A4, 0x44000402, 0x0),
+
+ // LFRAME#
+ _PAD_CFG_STRUCT(GPP_A5, 0x44000600, 0x0),
+
+ // SERIRQ
+ _PAD_CFG_STRUCT(GPP_A6, 0x44000402, 0x0),
+
+ // PIRQA#
+ _PAD_CFG_STRUCT(GPP_A7, 0x44000102, 0x0),
+
+ // CLKRUN#
+ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0),
+
+ // CLKOUT_LPC0
+ _PAD_CFG_STRUCT(GPP_A9, 0x44000600, 0x0),
+
+ // CLKOUT_LPC1
+ _PAD_CFG_STRUCT(GPP_A10, 0x44000600, 0x1000),
+
+ // PME#
+ _PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0),
+
+ // BM_BUSY#
+ _PAD_CFG_STRUCT(GPP_A12, 0x44000200, 0x0),
+
+ // SUSWARN#/SUSPWRDNACK
+ _PAD_CFG_STRUCT(GPP_A13, 0x44000200, 0x0),
+
+ // SUS_STAT#/ESPI_RESET#
+ _PAD_CFG_STRUCT(GPP_A14, 0x44000600, 0x0),
+
+ // SUS_ACK#
+ _PAD_CFG_STRUCT(GPP_A15, 0x44000502, 0x0),
+
+ // SD_1P8_SEL
+ _PAD_CFG_STRUCT(GPP_A16, 0x44000200, 0x0),
+
+ // SD_PWR_EN#
+ _PAD_CFG_STRUCT(GPP_A17, 0x44000200, 0x0),
+
+ // ISH_GP0
+ _PAD_CFG_STRUCT(GPP_A18, 0x44000201, 0x0),
+
+ // ISH_GP1
+ _PAD_CFG_STRUCT(GPP_A19, 0x44000603, 0x0),
+
+ // ISH_GP2
+ _PAD_CFG_STRUCT(GPP_A20, 0x44000200, 0x0),
+
+ // ISH_GP3
+ _PAD_CFG_STRUCT(GPP_A21, 0x84000200, 0x1000),
+
+ // ISH_GP4
+ _PAD_CFG_STRUCT(GPP_A22, 0x4000200, 0x0),
+
+ // ISH_GP5
+ _PAD_CFG_STRUCT(GPP_A23, 0x4000200, 0x0),
+
+ // CORE_VID0
+ _PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0),
+
+ // CORE_VID1
+ _PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0),
+
+ // VRALERT#
+ _PAD_CFG_STRUCT(GPP_B2, 0x44000200, 0x0),
+
+ // CPU_GP2
+ _PAD_CFG_STRUCT(GPP_B3, 0x44000200, 0x0),
+
+ // CPU_GP3
+ _PAD_CFG_STRUCT(GPP_B4, 0x44000200, 0x0),
+
+ // SRCCLKREQ0#
+ _PAD_CFG_STRUCT(GPP_B5, 0x44000200, 0x0),
+
+ // SRCCLKREQ1#
+ _PAD_CFG_STRUCT(GPP_B6, 0x44000200, 0x0),
+
+ // SRCCLKREQ2#
+ _PAD_CFG_STRUCT(GPP_B7, 0x44000700, 0x0),
+
+ // SRCCLKREQ3#
+ _PAD_CFG_STRUCT(GPP_B8, 0x44000700, 0x0),
+
+ // SRCCLKREQ4#
+ _PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x0),
+
+ // SRCCLKREQ5#
+ _PAD_CFG_STRUCT(GPP_B10, 0x44000702, 0x0),
+
+ // EXT_PWR_GATE#
+ _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0),
+
+ // SLP_S0#
+ _PAD_CFG_STRUCT(GPP_B12, 0x44000200, 0x0),
+
+ // PLTRST#
+ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0),
+
+ // SPKR
+ _PAD_CFG_STRUCT(GPP_B14, 0x44000600, 0x1000),
+
+ // GSPI0_CS#
+ _PAD_CFG_STRUCT(GPP_B15, 0x44000200, 0x0),
+
+ // GSPI0_CLK
+ _PAD_CFG_STRUCT(GPP_B16, 0x44000200, 0x0),
+
+ // GSPI0_MISO
+ _PAD_CFG_STRUCT(GPP_B17, 0x44000200, 0x0),
+
+ // GSPI0_MOSI
+ _PAD_CFG_STRUCT(GPP_B18, 0x44000600, 0x3000),
+
+ // GSPI1_CS#
+ _PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0),
+
+ // GSPI1_CLK
+ _PAD_CFG_STRUCT(GPP_B20, 0x44000200, 0x0),
+
+ // GSPI1_MISO
+ _PAD_CFG_STRUCT(GPP_B21, 0x44000200, 0x0),
+
+ // GSPI1_MOSI
+ _PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000),
+
+ // SML1ALERT#/PCHHOT#
+ _PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0),
+
+ // SMBCLK
+ _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0),
+
+ // SMBDATA
+ _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000),
+
+ // SMBALERT#
+ _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000),
+
+ // SML0CLK
+ _PAD_CFG_STRUCT(GPP_C3, 0x44000200, 0x0),
+
+ // SML0DATA
+ _PAD_CFG_STRUCT(GPP_C4, 0x44000200, 0x0),
+
+ // SML0ALERT#
+ _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0),
+
+ // SML1CLK
+// _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00),
+
+ // SML1DATA
+// _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00),
+
+ // UART0_RXD
+ _PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x0),
+
+ // UART0_TXD
+ _PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0),
+
+ // UART0_RTS#
+ _PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0),
+
+ // UART0_CTS#
+ _PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x0),
+
+ // UART1_RXD
+ _PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0),
+
+ // UART1_TXD
+ _PAD_CFG_STRUCT(GPP_C13, 0x82880102, 0x0),
+
+ // UART1_RTS#
+ _PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0),
+
+ // UART1_CTS#
+ _PAD_CFG_STRUCT(GPP_C15, 0x44000700, 0x0),
+
+ // I2C0_SDA
+ _PAD_CFG_STRUCT(GPP_C16, 0x44000200, 0x0),
+
+ // I2C0_SCL
+ _PAD_CFG_STRUCT(GPP_C17, 0x44000200, 0x0),
+
+ // I2C1_SDA
+ _PAD_CFG_STRUCT(GPP_C18, 0x44000200, 0x0),
+
+ // I2C1_SCL
+ _PAD_CFG_STRUCT(GPP_C19, 0x40880102, 0x0),
+
+ // UART2_RXD
+ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0),
+
+ // UART2_TXD
+ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0),
+
+ // UART2_RTS#
+ _PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0),
+
+ // UART2_CTS#
+ _PAD_CFG_STRUCT(GPP_C23, 0x44000700, 0x0),
+
+ // SPI1_CS#
+ _PAD_CFG_STRUCT(GPP_D0, 0x44000200, 0x0),
+
+ // SPI1_CLK
+ _PAD_CFG_STRUCT(GPP_D1, 0x44000200, 0x0),
+
+ // SPI1_MISO
+ _PAD_CFG_STRUCT(GPP_D2, 0x44000200, 0x0),
+
+ // SPI1_MOSI
+ _PAD_CFG_STRUCT(GPP_D3, 0x44000200, 0x0),
+
+ // FLASHTRIG
+ _PAD_CFG_STRUCT(GPP_D4, 0x44000200, 0x0),
+
+ // ISH_I2C0_SDA
+ _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0),
+
+ // ISH_I2C0_SCL
+ _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0),
+
+ // ISH_I2C1_SDA
+ _PAD_CFG_STRUCT(GPP_D7, 0x44000700, 0x0),
+
+ // ISH_I2C1_SCL
+ _PAD_CFG_STRUCT(GPP_D8, 0x44000201, 0x0),
+
+ // GPIO
+ _PAD_CFG_STRUCT(GPP_D9, 0x44000200, 0x0),
+
+ // GPIO
+ _PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x0),
+
+ // GPIO
+ _PAD_CFG_STRUCT(GPP_D11, 0x44000200, 0x0),
+
+ // GPIO
+ _PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x0),
+
+ // ISH_UART0_RXD
+ _PAD_CFG_STRUCT(GPP_D13, 0x44000200, 0x0),
+
+ // ISH_UART0_TXD
+ _PAD_CFG_STRUCT(GPP_D14, 0x44000200, 0x0),
+
+ // ISH_UART0_RTS#
+ _PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0),
+
+ // ISH_UART0_CTS#
+ _PAD_CFG_STRUCT(GPP_D16, 0x44000700, 0x0),
+
+ // DMIC_CLK1
+ _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0),
+
+ // DMIC_DATA1
+ _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0),
+
+ // DMIC_CLK0
+ _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0),
+
+ // DMIC_DATA0
+ _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0),
+
+ // SPI1_IO2
+ _PAD_CFG_STRUCT(GPP_D21, 0x44000102, 0x0),
+
+ // SPI1_IO3
+ _PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0),
+
+ // I2S_MCLK
+ _PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0),
+
+ // SATAXPCIE0/SATAGP0
+ _PAD_CFG_STRUCT(GPP_E0, 0x42100100, 0x1000),
+
+ // SATAXPCIE1/SATAGP1
+ _PAD_CFG_STRUCT(GPP_E1, 0x44000702, 0x0),
+
+ // SATAXPCIE2/SATAGP2
+ _PAD_CFG_STRUCT(GPP_E2, 0x44000502, 0x0),
+
+ // CPU_GP0
+ _PAD_CFG_STRUCT(GPP_E3, 0x40000000, 0x0),
+
+ // DEVSLP0
+ _PAD_CFG_STRUCT(GPP_E4, 0x4000700, 0x0),
+
+ // DEVSLP1
+ _PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0),
+
+ // DEVSLP2
+ _PAD_CFG_STRUCT(GPP_E6, 0x44000200, 0x0),
+
+ // CPU_GP1
+ _PAD_CFG_STRUCT(GPP_E7, 0x44000100, 0x0),
+
+ // SATALED#
+ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0),
+
+ // USB2_OC0#
+ _PAD_CFG_STRUCT(GPP_E9, 0x44000200, 0x0),
+
+ // USB2_OC1#
+ _PAD_CFG_STRUCT(GPP_E10, 0x44000200, 0x0),
+
+ // USB2_OC2#
+ _PAD_CFG_STRUCT(GPP_E11, 0x44000200, 0x0),
+
+ // USB2_OC3#
+ _PAD_CFG_STRUCT(GPP_E12, 0x44000200, 0x0),
+
+ // DDPB_HPD0
+ _PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0),
+
+ // DDPC_HPD1
+ _PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0),
+
+ // DDPD_HPD2
+ _PAD_CFG_STRUCT(GPP_E15, 0x42840102, 0x0),
+
+ // DDPE_HPD3
+ _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x0),
+
+ // EDP_HPD
+ _PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0),
+
+ // DDPB_CTRLCLK
+ _PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x0),
+
+ // DDPB_CTRLDATA
+ _PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000),
+
+ // DDPC_CTRLCLK
+ _PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x0),
+
+ // DDPC_CTRLDATA
+ _PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000),
+
+ // DDPD_CTRLCLK
+ _PAD_CFG_STRUCT(GPP_E22, 0x40100000, 0x0),
+
+ // DDPD_CTRLDATA
+ _PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000),
+
+ // BATLOW#
+ _PAD_CFG_STRUCT(GPD0, 0x4000702, 0x0),
+
+ // LANPHYPC
+ _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x0),
+
+ // LAN_WAKE#
+ _PAD_CFG_STRUCT(GPD2, 0x880502, 0x0),
+
+ // PWRBTN#
+ _PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000),
+
+ // SLP_S3#
+ _PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0),
+
+ // SLP_S4#
+ _PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0),
+
+ // SLP_A#
+ _PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0),
+
+ // RSVD
+ _PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0),
+
+ // SUSCLK
+ _PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0),
+
+ // SLP_WLAN#
+ _PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0),
+
+ // SLP_S5#
+ _PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0),
+
+ // LANPHYPC
+ _PAD_CFG_STRUCT(GPD11, 0x4000500, 0x0),
+
+ // I2S2_SCLK
+ _PAD_CFG_STRUCT(GPP_F0, 0x44000702, 0x0),
+
+ // I2S2_SFRM
+ _PAD_CFG_STRUCT(GPP_F1, 0x44000702, 0x0),
+
+ // I2S2_TXD
+ _PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0),
+
+ // I2S2_RXD
+ _PAD_CFG_STRUCT(GPP_F3, 0x44000702, 0x0),
+
+ // I2C2_SDA
+ _PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2000000),
+
+ // I2C2_SCL
+ _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2000000),
+
+ // I2C3_SDA
+ _PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2000000),
+
+ // I2C3_SCL
+ _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2000000),
+
+ // I2C4_SDA
+ _PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2000000),
+
+ // I2C4_SCL
+ _PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2000000),
+
+ // I2C5_SDA/ISH_I2C2_SDA
+ _PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2000000),
+
+ // I2C5_SCL/ISH_I2C2_SCL
+ _PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2000000),
+
+ // EMMC_CMD
+ _PAD_CFG_STRUCT(GPP_F12, 0x44000702, 0x0),
+
+ // EMMC_DATA0
+ _PAD_CFG_STRUCT(GPP_F13, 0x44000702, 0x0),
+
+ // EMMC_DATA1
+ _PAD_CFG_STRUCT(GPP_F14, 0x44000702, 0x0),
+
+ // EMMC_DATA2
+ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x0),
+
+ // EMMC_DATA3
+ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x0),
+
+ // EMMC_DATA4
+ _PAD_CFG_STRUCT(GPP_F17, 0x44000702, 0x0),
+
+ // EMMC_DATA5
+ _PAD_CFG_STRUCT(GPP_F18, 0x44000702, 0x0),
+
+ // EMMC_DATA6
+ _PAD_CFG_STRUCT(GPP_F19, 0x44000702, 0x0),
+
+ // EMMC_DATA7
+ _PAD_CFG_STRUCT(GPP_F20, 0x44000702, 0x0),
+
+ // EMMC_RCLK
+ _PAD_CFG_STRUCT(GPP_F21, 0x44000702, 0x0),
+
+ // EMMC_CLK
+ _PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0),
+
+ // GPIO
+ _PAD_CFG_STRUCT(GPP_F23, 0x40100100, 0x0),
+
+ // SD_CMD
+ _PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0),
+
+ // SD_DATA0
+ _PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x0),
+
+ // SD_DATA1
+ _PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0),
+
+ // SD_DATA2
+ _PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0),
+
+ // SD_DATA3
+ _PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0),
+
+ // SD_CD#
+ _PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0),
+
+ // SD_CLK
+ _PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0),
+
+ // SD_WP
+ _PAD_CFG_STRUCT(GPP_G7, 0x44000702, 0x0)
+};
+
+void mainboard_configure_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c
new file mode 100644
index 0000000..00246a4
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+ // UART2_RXD
+ _PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x0),
+
+ // UART2_TXD
+ _PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0)
+};
+
+void mainboard_configure_gpios(void)
+{
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c
new file mode 100644
index 0000000..05bb273
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* Realtek ALC269VC */
+ 0x10ec0269,
+ 0x15581314,
+ 11,
+ AZALIA_SUBVENDOR(0, 0x15581314),
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170120),
+ AZALIA_PIN_CFG(0, 0x15, 0x02211010),
+ AZALIA_PIN_CFG(0, 0x17, 0x40000000),
+ AZALIA_PIN_CFG(0, 0x18, 0x02a11030),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+ /* Intel iGPU HDMI */
+ 0x8086280b,
+ 0x80860101,
+ 4,
+ AZALIA_SUBVENDOR(2, 0x80860101),
+ AZALIA_PIN_CFG(2, 0x5, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x6, 0x18560010),
+ AZALIA_PIN_CFG(2, 0x7, 0x18560010)
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;