| # SPDX-License-Identifier: GPL-2.0-only |
| |
| chip soc/intel/skylake |
| register "panel_cfg" = "{ |
| .up_delay_ms = 200, // T3 |
| .down_delay_ms = 0, // T10 |
| .cycle_delay_ms = 500, // T12 |
| .backlight_on_delay_ms = 50, // T7 |
| .backlight_off_delay_ms = 0, // T9 |
| .backlight_pwm_hz = 200, |
| }" |
| |
| # IGD Displays |
| register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| |
| # FSP Configuration |
| register "SkipExtGfxScan" = "1" |
| register "SaGv" = "SaGv_Enabled" |
| register "eist_enable" = "1" |
| |
| register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| register "PmConfigSlpS4MinAssert" = "1" # 1s |
| register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| register "PmConfigSlpAMinAssert" = "3" # 2s |
| |
| # Send an extra VR mailbox command for the PS4 exit issue |
| register "SendVrMbxCmd" = "2" |
| |
| register "power_limits_config" = "{ |
| .tdp_pl1_override = 20, |
| .tdp_pl2_override = 30, |
| }" |
| |
| register "SerialIoDevMode" = "{ |
| [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART |
| }" |
| |
| device domain 0 on |
| subsystemid 0x1558 0x1313 inherit |
| device ref system_agent on end |
| device ref igpu on end |
| device ref sa_thermal on end |
| device ref south_xhci on |
| # USB2 |
| register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right |
| register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE |
| register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right |
| register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
| register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth |
| register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A, left |
| register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right |
| # USB3 |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G |
| register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right |
| register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left |
| end |
| device ref thermal on end |
| device ref heci1 on end |
| device ref sata on |
| # Ports |
| register "SataPortsEnable[0]" = "1" |
| register "SataPortsEnable[2]" = "1" |
| register "SataPortsDevSlp[2]" = "1" |
| end |
| device ref uart2 on end |
| device ref pcie_rp1 on |
| device pci 00.0 on end # x4 TBT |
| register "PcieRpEnable[0]" = "1" |
| register "PcieRpClkReqSupport[0]" = "1" |
| register "PcieRpClkReqNumber[0]" = "4" |
| register "PcieRpClkSrcNumber[0]" = "4" |
| register "PcieRpHotPlug[0]" = "1" |
| register "PcieRpLtrEnable[0]" = "1" |
| smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" |
| end |
| device ref pcie_rp5 on |
| device pci 00.0 on end # x1 LAN |
| register "PcieRpEnable[4]" = "1" |
| register "PcieRpClkReqSupport[4]" = "1" |
| register "PcieRpClkReqNumber[4]" = "3" |
| register "PcieRpClkSrcNumber[4]" = "3" |
| register "PcieRpLtrEnable[4]" = "1" |
| end |
| device ref pcie_rp6 on |
| device pci 00.0 on end # x1 WLAN |
| register "PcieRpEnable[5]" = "1" |
| register "PcieRpClkReqSupport[5]" = "1" |
| register "PcieRpClkReqNumber[5]" = "2" |
| register "PcieRpClkSrcNumber[5]" = "2" |
| register "PcieRpLtrEnable[5]" = "1" |
| smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" |
| end |
| device ref pcie_rp9 on |
| device pci 00.0 on end # x4 M.2/M (J_SSD1) |
| register "PcieRpEnable[8]" = "1" |
| register "PcieRpClkReqSupport[8]" = "1" |
| register "PcieRpClkReqNumber[8]" = "5" |
| register "PcieRpClkSrcNumber[8]" = "5" |
| register "PcieRpLtrEnable[8]" = "1" |
| smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" |
| end |
| device ref lpc_espi on |
| register "gen1_dec" = "0x000c0681" |
| register "gen2_dec" = "0x000c1641" |
| register "gen3_dec" = "0x00040069" |
| register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| chip drivers/pc80/tpm |
| device pnp 0c31.0 on end |
| end |
| end |
| device ref p2sb hidden end |
| device ref pmc on |
| register "gpe0_dw0" = "GPP_C" |
| register "gpe0_dw1" = "GPP_D" |
| register "gpe0_dw2" = "GPP_E" |
| end |
| device ref hda on end |
| device ref smbus on end |
| device ref fast_spi on end |
| end |
| end |