| chip soc/intel/alderlake |
| |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route. i.e. If this route changes then the affected GPE |
| # offset bits also need to be changed. |
| register "pmc_gpe0_dw0" = "GPP_B" |
| register "pmc_gpe0_dw1" = "GPP_D" |
| register "pmc_gpe0_dw2" = "GPP_E" |
| |
| # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| register "gen1_dec" = "0x00fc0801" |
| register "gen2_dec" = "0x000c0201" |
| # EC memory map range is 0x900-0x9ff |
| register "gen3_dec" = "0x00fc0901" |
| |
| # USB configuration |
| register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" |
| register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" |
| register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" |
| register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" |
| register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" |
| register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" |
| register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" |
| register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" |
| |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" |
| register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" |
| register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" |
| |
| register "sata_salp_support" = "1" |
| |
| register "sata_ports_enable" = "{ |
| [0] = 1, |
| [1] = 1, |
| }" |
| |
| register "sata_ports_dev_slp" = "{ |
| [0] = 1, |
| [1] = 1, |
| }" |
| |
| register "serial_io_uart_mode" = "{ |
| [PchSerialIoIndexUART0] = PchSerialIoSkipInit, |
| [PchSerialIoIndexUART1] = PchSerialIoPci, |
| [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| }" |
| |
| # Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80) |
| # Clock source is shared hence marked as free running. |
| register "pch_pcie_rp[PCH_RP(5)]" = "{ |
| .flags = PCIE_RP_CLK_SRC_UNUSED, |
| }" |
| register "pch_pcie_rp[PCH_RP(6)]" = "{ |
| .flags = PCIE_RP_CLK_SRC_UNUSED, |
| }" |
| register "pch_pcie_rp[PCH_RP(7)]" = "{ |
| .flags = PCIE_RP_CLK_SRC_UNUSED, |
| }" |
| register "pch_pcie_rp[PCH_RP(8)]" = "{ |
| .flags = PCIE_RP_CLK_SRC_UNUSED, |
| }" |
| register "pch_pcie_rp[PCH_RP(9)]" = "{ |
| .flags = PCIE_RP_CLK_SRC_UNUSED, |
| }" |
| register "pch_pcie_rp[PCH_RP(10)]" = "{ |
| .flags = PCIE_RP_CLK_SRC_UNUSED, |
| .pcie_rp_aspm = ASPM_DISABLE, |
| }" |
| register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" |
| register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING" |
| |
| # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80) |
| # Clock source is shared hence marked as free running. |
| register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, |
| }" |
| register "cpu_pcie_rp[CPU_RP(2)]" = "{ |
| .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, |
| }" |
| register "cpu_pcie_rp[CPU_RP(3)]" = "{ |
| .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, |
| }" |
| |
| device domain 0 on |
| device ref pcie5 on end |
| device ref igpu on end |
| device ref dtt on end |
| device ref pcie4_0 on end |
| device ref pcie4_1 on end |
| device ref crashlog off end |
| device ref xhci on end |
| device ref heci1 on end |
| device ref sata on end |
| device ref pcie_rp5 on end |
| device ref pcie_rp6 on end |
| device ref pcie_rp8 on end |
| device ref pcie_rp9 on end |
| device ref pcie_rp10 on end |
| device ref uart0 on end |
| device ref uart1 on end |
| device ref p2sb on end |
| device ref hda on end |
| device ref smbus on end |
| end |
| end |