| menu "Console" |
| |
| config BOOTBLOCK_CONSOLE |
| bool "Enable early (bootblock) console output." |
| depends on ARCH_ARMV7 |
| default n |
| help |
| Use console during the bootblock if supported |
| |
| config EARLY_CONSOLE |
| bool "Enable early (pre-RAM) console output." |
| default y if CACHE_AS_RAM |
| default n |
| help |
| Use console during early (pre-RAM) boot stages |
| |
| config SQUELCH_EARLY_SMP |
| bool "Squelch AP CPUs from early console." |
| default y |
| depends on EARLY_CONSOLE |
| help |
| When selected only the BSP CPU will output to early console. |
| |
| Console drivers have unpredictable behaviour if multiple threads |
| attempt to share the same resources without a spinlock. |
| |
| If unsure, say Y. |
| |
| config CONSOLE_SERIAL |
| bool "Serial port console output" |
| default y |
| help |
| Send coreboot debug output to a serial port (should be one or more of |
| CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART) |
| |
| config CONSOLE_SERIAL8250 |
| bool "Serial port console output (I/O mapped, 8250-compatible)" |
| depends on CONSOLE_SERIAL |
| depends on HAVE_UART_IO_MAPPED |
| default y |
| help |
| Send coreboot debug output to an I/O mapped serial port console. |
| |
| config CONSOLE_SERIAL8250MEM |
| bool "Serial port console output (memory mapped, 8250-compatible)" |
| depends on CONSOLE_SERIAL |
| depends on HAVE_UART_MEMORY_MAPPED |
| help |
| Send coreboot debug output to a memory mapped serial port console. |
| |
| config CONSOLE_SERIAL_UART |
| bool "Serial port console output (device-specific UART)" |
| depends on CONSOLE_SERIAL |
| depends on HAVE_UART_SPECIAL |
| default y |
| help |
| Send coreboot debug output to a device-specific serial port console. |
| |
| choice |
| prompt "Serial port for 8250" |
| default CONSOLE_SERIAL_COM1 |
| depends on CONSOLE_SERIAL8250 |
| |
| config CONSOLE_SERIAL_COM1 |
| bool "COM1/ttyS0, I/O port 0x3f8" |
| help |
| Serial console on COM1/ttyS0 at I/O port 0x3f8. |
| config CONSOLE_SERIAL_COM2 |
| bool "COM2/ttyS1, I/O port 0x2f8" |
| help |
| Serial console on COM2/ttyS1 at I/O port 0x2f8. |
| config CONSOLE_SERIAL_COM3 |
| bool "COM3/ttyS2, I/O port 0x3e8" |
| help |
| Serial console on COM3/ttyS2 at I/O port 0x3e8. |
| config CONSOLE_SERIAL_COM4 |
| bool "COM4/ttyS3, I/O port 0x2e8" |
| help |
| Serial console on COM4/ttyS3 at I/O port 0x2e8. |
| |
| endchoice |
| |
| config TTYS0_BASE |
| hex |
| depends on CONSOLE_SERIAL8250 |
| default 0x3f8 if CONSOLE_SERIAL_COM1 |
| default 0x2f8 if CONSOLE_SERIAL_COM2 |
| default 0x3e8 if CONSOLE_SERIAL_COM3 |
| default 0x2e8 if CONSOLE_SERIAL_COM4 |
| help |
| Map the COM port names to the respective I/O port. |
| |
| choice |
| prompt "Baud rate" |
| default CONSOLE_SERIAL_115200 |
| depends on CONSOLE_SERIAL |
| |
| config CONSOLE_SERIAL_115200 |
| bool "115200" |
| help |
| Set serial port Baud rate to 115200. |
| config CONSOLE_SERIAL_57600 |
| bool "57600" |
| help |
| Set serial port Baud rate to 57600. |
| config CONSOLE_SERIAL_38400 |
| bool "38400" |
| help |
| Set serial port Baud rate to 38400. |
| config CONSOLE_SERIAL_19200 |
| bool "19200" |
| help |
| Set serial port Baud rate to 19200. |
| config CONSOLE_SERIAL_9600 |
| bool "9600" |
| help |
| Set serial port Baud rate to 9600. |
| |
| endchoice |
| |
| #FIXME(dhendrix): Change name to SERIAL_BAUD? (Stefan sayz: yes!!) |
| config TTYS0_BAUD |
| int |
| default 115200 if CONSOLE_SERIAL_115200 |
| default 57600 if CONSOLE_SERIAL_57600 |
| default 38400 if CONSOLE_SERIAL_38400 |
| default 19200 if CONSOLE_SERIAL_19200 |
| default 9600 if CONSOLE_SERIAL_9600 |
| help |
| Map the Baud rates to an integer. |
| |
| # TODO: Allow user-friendly selection of settings other than 8n1. |
| config TTYS0_LCS |
| int |
| default 3 |
| depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM |
| |
| config SPKMODEM |
| bool "spkmodem (console on speaker) console output" |
| default n |
| help |
| Send coreboot debug output through speaker |
| |
| # Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code. |
| config HAVE_USBDEBUG |
| bool |
| default y if HAVE_USBDEBUG_OPTIONS |
| default n |
| |
| # Use "select HAVE_USBDEBUG_OPTIONS" on southbridges with multiple |
| # EHCI controllers or multiple ports with Debug Port capability |
| config HAVE_USBDEBUG_OPTIONS |
| def_bool n |
| |
| config USBDEBUG |
| bool "USB 2.0 EHCI debug dongle support" |
| default n |
| depends on HAVE_USBDEBUG |
| help |
| This option allows you to use a so-called USB EHCI Debug device |
| (such as the Ajays NET20DC, AMIDebug RX, or a system using the |
| Linux "EHCI Debug Device gadget" driver found in recent kernel) |
| to retrieve the coreboot debug messages (instead, or in addition |
| to, a serial port). |
| |
| This feature is NOT supported on all chipsets in coreboot! |
| |
| It also requires a USB2 controller which supports the EHCI |
| Debug Port capability. |
| |
| See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list |
| of supported controllers. |
| |
| If unsure, say N. |
| |
| config USBDEBUG_IN_ROMSTAGE |
| bool |
| default y if USBDEBUG && EARLY_CBMEM_INIT && EARLY_CONSOLE |
| default n |
| |
| if USBDEBUG |
| |
| config USBDEBUG_HCD_INDEX |
| int "Index for EHCI controller to use with usbdebug" |
| default 0 |
| help |
| Some boards have multiple EHCI controllers with possibly only |
| one having the Debug Port capability on an external USB port. |
| |
| Mapping of this index to PCI device functions is southbridge |
| specific and mainboard level Kconfig should already provide |
| a working default value here. |
| |
| config USBDEBUG_DEFAULT_PORT |
| int "Default USB port to use as Debug Port" |
| default 0 |
| help |
| Selects which physical USB port usbdebug dongle is connected to. |
| Setting of 0 means to scan possible ports starting from 1. |
| |
| Intel platforms have hardwired the debug port location and this |
| setting makes no difference there. |
| |
| Hence, if you select the correct port here, you can speed up |
| your boot time. Which USB port number refers to which actual |
| port on your mainboard (potentially also USB pin headers on |
| your mainboard) is highly board-specific, and you'll likely |
| have to find out by trial-and-error. |
| |
| choice |
| prompt "Type of dongle" |
| default USBDEBUG_DONGLE_STD |
| |
| config USBDEBUG_DONGLE_STD |
| bool "Net20DC or compatible" |
| |
| config USBDEBUG_DONGLE_BEAGLEBONE |
| bool "BeagleBone" |
| help |
| Use this to configure the USB hub on BeagleBone board. |
| |
| endchoice |
| |
| config USBDEBUG_OPTIONAL_HUB_PORT |
| int |
| default 2 if USBDEBUG_DONGLE_BEAGLEBONE |
| default 0 |
| |
| endif # USBDEBUG |
| |
| # TODO: Deps? |
| # TODO: Improve description. |
| config ONBOARD_VGA_IS_PRIMARY |
| bool "Use onboard VGA as primary video device" |
| default n |
| help |
| If not selected, the last adapter found will be used. |
| |
| config CONSOLE_NE2K |
| bool "Network console over NE2000 compatible Ethernet adapter" |
| default n |
| help |
| Send coreboot debug output to a Ethernet console, it works |
| same way as Linux netconsole, packets are received to UDP |
| port 6666 on IP/MAC specified with options bellow. |
| Use following netcat command: nc -u -l -p 6666 |
| |
| config CONSOLE_NE2K_DST_MAC |
| depends on CONSOLE_NE2K |
| string "Destination MAC address of remote system" |
| default "00:13:d4:76:a2:ac" |
| help |
| Type in either MAC address of logging system or MAC address |
| of the router. |
| |
| config CONSOLE_NE2K_DST_IP |
| depends on CONSOLE_NE2K |
| string "Destination IP of logging system" |
| default "10.0.1.27" |
| help |
| This is IP adress of the system running for example |
| netcat command to dump the packets. |
| |
| config CONSOLE_NE2K_SRC_IP |
| depends on CONSOLE_NE2K |
| string "IP address of coreboot system" |
| default "10.0.1.253" |
| help |
| This is the IP of the coreboot system |
| |
| config CONSOLE_NE2K_IO_PORT |
| depends on CONSOLE_NE2K |
| hex "NE2000 adapter fixed IO port address" |
| default 0xe00 |
| help |
| This is the IO port address for the IO port |
| on the card, please select some non-conflicting region, |
| 32 bytes of IO spaces will be used (and align on 32 bytes |
| boundary, qemu needs broader align) |
| |
| config CONSOLE_CBMEM |
| bool "Send console output to a CBMEM buffer" |
| default n |
| help |
| Enable this to save the console output in a CBMEM buffer. This would |
| allow to see coreboot console output from Linux space. |
| |
| config CONSOLE_CBMEM_BUFFER_SIZE |
| depends on CONSOLE_CBMEM |
| hex "Room allocated for console output in CBMEM" |
| default 0x10000 |
| help |
| Space allocated for console output storage in CBMEM. The default |
| value (64K or 0x10000 bytes) is large enough to accommodate |
| even the BIOS_SPEW level. |
| |
| config CONSOLE_CAR_BUFFER_SIZE |
| depends on CONSOLE_CBMEM |
| hex "Room allocated for console output in Cache as RAM" |
| default 0xc00 |
| help |
| Console is used before RAM is initialized. This is the room reserved |
| in the DCACHE based RAM to keep console output before it can be |
| saved in a CBMEM buffer. 3K bytes should be enough even for the |
| BIOS_SPEW level. |
| |
| config CONSOLE_QEMU_DEBUGCON |
| bool "QEMU debug console output" |
| depends on BOARD_EMULATION_QEMU_X86 |
| default y |
| help |
| Send coreboot debug output to QEMU's isa-debugcon device: |
| |
| qemu-system-x86_64 \ |
| -chardev file,id=debugcon,path=/dir/file.log \ |
| -device isa-debugcon,iobase=0x402,chardev=debugcon |
| |
| config CONSOLE_QEMU_DEBUGCON_PORT |
| hex "QEMU debug console port" |
| depends on CONSOLE_QEMU_DEBUGCON |
| default 0x402 |
| |
| choice |
| prompt "Default console log level" |
| default DEFAULT_CONSOLE_LOGLEVEL_8 |
| |
| config DEFAULT_CONSOLE_LOGLEVEL_8 |
| bool "8: SPEW" |
| help |
| Way too many details. |
| config DEFAULT_CONSOLE_LOGLEVEL_7 |
| bool "7: DEBUG" |
| help |
| Debug-level messages. |
| config DEFAULT_CONSOLE_LOGLEVEL_6 |
| bool "6: INFO" |
| help |
| Informational messages. |
| config DEFAULT_CONSOLE_LOGLEVEL_5 |
| bool "5: NOTICE" |
| help |
| Normal but significant conditions. |
| config DEFAULT_CONSOLE_LOGLEVEL_4 |
| bool "4: WARNING" |
| help |
| Warning conditions. |
| config DEFAULT_CONSOLE_LOGLEVEL_3 |
| bool "3: ERR" |
| help |
| Error conditions. |
| config DEFAULT_CONSOLE_LOGLEVEL_2 |
| bool "2: CRIT" |
| help |
| Critical conditions. |
| config DEFAULT_CONSOLE_LOGLEVEL_1 |
| bool "1: ALERT" |
| help |
| Action must be taken immediately. |
| config DEFAULT_CONSOLE_LOGLEVEL_0 |
| bool "0: EMERG" |
| help |
| System is unusable. |
| |
| endchoice |
| |
| config DEFAULT_CONSOLE_LOGLEVEL |
| int |
| default 0 if DEFAULT_CONSOLE_LOGLEVEL_0 |
| default 1 if DEFAULT_CONSOLE_LOGLEVEL_1 |
| default 2 if DEFAULT_CONSOLE_LOGLEVEL_2 |
| default 3 if DEFAULT_CONSOLE_LOGLEVEL_3 |
| default 4 if DEFAULT_CONSOLE_LOGLEVEL_4 |
| default 5 if DEFAULT_CONSOLE_LOGLEVEL_5 |
| default 6 if DEFAULT_CONSOLE_LOGLEVEL_6 |
| default 7 if DEFAULT_CONSOLE_LOGLEVEL_7 |
| default 8 if DEFAULT_CONSOLE_LOGLEVEL_8 |
| help |
| Map the log level config names to an integer. |
| |
| config CONSOLE_LOGBUF |
| bool |
| default n |
| |
| config NO_POST |
| bool "Don't show any POST codes" |
| default n |
| |
| |
| config CONSOLE_POST |
| bool "Show POST codes on the debug console" |
| depends on !NO_POST |
| default n |
| help |
| If enabled, coreboot will additionally print POST codes (which are |
| usually displayed using a so-called "POST card" ISA/PCI/PCI-E |
| device) on the debug console. |
| |
| config CMOS_POST |
| bool "Store post codes in CMOS for debugging" |
| depends on !NO_POST && PC80_SYSTEM |
| default n |
| help |
| If enabled, coreboot will store post codes in CMOS and switch between |
| two offsets on each boot so the last post code in the previous boot |
| can be retrieved. This uses 3 bytes of CMOS. |
| |
| config CMOS_POST_OFFSET |
| hex "Offset into CMOS to store POST codes" |
| depends on CMOS_POST |
| default 0 |
| help |
| If CMOS_POST is enabled then an offset into CMOS must be provided. |
| If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value |
| defined in the mainboard option table. |
| |
| config CMOS_POST_EXTRA |
| bool "Store extra logging info into CMOS" |
| depends on CMOS_POST |
| default n |
| help |
| This will enable extra logging of work that happens between post |
| codes into CMOS for debug. This uses an additional 8 bytes of CMOS. |
| |
| config IO_POST |
| bool "Send POST codes to an IO port" |
| depends on PC80_SYSTEM |
| default y |
| help |
| If enabled, POST codes will be written to an IO port. |
| |
| config IO_POST_PORT |
| depends on IO_POST |
| hex "IO port for POST codes" |
| default 0x80 |
| help |
| POST codes on x86 are typically written to the LPC bus on port |
| 0x80. However, it may be desireable to change the port number |
| depending on the presence of coprocessors/microcontrollers or if the |
| platform does not support IO in the conventional x86 manner. |
| |
| endmenu |