| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <cpu/x86/mtrr.h> |
| #include <cpu/amd/msr.h> |
| #include <northbridge/amd/agesa/agesa_helper.h> |
| #include <AGESA.h> |
| #include "amdlib.h" |
| |
| void amd_initcpuio(void) |
| { |
| UINT64 MsrReg; |
| UINT32 PciData; |
| PCI_ADDR PciAddress; |
| AMD_CONFIG_PARAMS StdHeader; |
| |
| /* Enable MMIO on AMD CPU Address Map Controller */ |
| |
| /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */ |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); |
| PciData = 0x00000B00; |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); |
| PciData = 0x00000A03; |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| |
| /* Set TOM-DFFFFFFF to Node0 Link0. */ |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); |
| PciData = 0x00DFFF00; |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); |
| MsrReg = (MsrReg >> 8) | 3; |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); |
| PciData = (UINT32) MsrReg; |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| |
| /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */ |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xBC); |
| PciData = 0x00FFFF00 | 0x80; |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8); |
| PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 03; |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| |
| /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */ |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); |
| //- PciData = 0x0000F000; |
| PciData = 0x00FFF000; |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); |
| PciData = 0x00000013; |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| } |
| |
| void amd_initmmio(void) |
| { |
| UINT64 MsrReg; |
| UINT32 PciData; |
| PCI_ADDR PciAddress; |
| AMD_CONFIG_PARAMS StdHeader; |
| |
| /* |
| Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base |
| Address MSR register. |
| */ |
| MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; |
| LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader); |
| |
| /* Enable Non-Post Memory in CPU */ |
| PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1; |
| PciData = (PciData >> 8) & ~0xff; |
| PciData |= 0x80; |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4); |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| |
| PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03); |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA0); |
| LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); |
| |
| /* Enable memory access */ |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); |
| LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); |
| PciData |= BIT1; |
| PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04); |
| LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); |
| |
| /* Set ROM cache onto WP to decrease post time */ |
| MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; |
| LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); |
| MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; |
| LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); |
| } |