src/soc/intel/xeon_sp/cpx/Kconfig

## SPDX-License-Identifier: GPL-2.0-only

if SOC_INTEL_COOPERLAKE_SP

config FSP_HEADER_PATH
	  string "Location of FSP headers"
	  depends on MAINBOARD_USES_FSP2_0
	  default "src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp"

config MAX_SOCKET
	int
	default 2

config MAX_CPUS
	int
	default 255

config PCR_BASE_ADDRESS
	hex
	default 0xfd000000
	help
	  This option allows you to select MMIO Base Address of sideband bus.

config DCACHE_RAM_BASE
	hex
	default 0xfe8b0000

config DCACHE_RAM_SIZE
	hex
	default 0x170000
	help
	  The size of the cache-as-ram region required during bootblock
	  and/or romstage.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0xA0000
	help
	  The amount of anticipated stack usage in CAR by bootblock and
	  other stages. It needs to include FSP-M stack requirement and
	  CB romstage stack requirement.

config CPU_MICROCODE_CBFS_LOC
	hex
	default 0xfff0fdc0

config CPU_MICROCODE_CBFS_LEN
	hex
	default 0x7C00

config C_ENV_BOOTBLOCK_SIZE
	hex
	default 0xC000

config HEAP_SIZE
	hex
	default 0x80000

config FSP_TEMP_RAM_SIZE
	hex
	depends on FSP_USES_CB_STACK
	default 0xA0000
	help
	  The amount of anticipated heap usage in CAR by FSP.
	  Refer to Platform FSP integration guide document to know
	  the exact FSP requirement for Heap setup.

config SOC_INTEL_COMMON_BLOCK_P2SB
	def_bool y

select CACHE_MRC_SETTINGS

# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
# Default value is set to one socket, full config.
config DIMM_MAX
	int
	default 12

# DDR4
config DIMM_SPD_SIZE
	int
	default 512

endif