| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering |
| ## Copyright (C) 2007-2009 coresystems GmbH |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| config NORTHBRIDGE_AMD_AMDFAM10 |
| bool |
| select HAVE_DEBUG_RAM_SETUP |
| select HAVE_DEBUG_SMBUS |
| select HAVE_DEBUG_CAR |
| select HYPERTRANSPORT_PLUGIN_SUPPORT |
| select MMCONF_SUPPORT |
| select PCIEXP_ASPM |
| select PCIEXP_COMMON_CLOCK |
| select PCIEXP_CLK_PM |
| select PCIEXP_L1_SUB_STATE |
| |
| if NORTHBRIDGE_AMD_AMDFAM10 |
| config AGP_APERTURE_SIZE |
| hex |
| default 0x4000000 |
| |
| config HW_MEM_HOLE_SIZEK |
| hex |
| default 0x100000 |
| |
| config HW_MEM_HOLE_SIZE_AUTO_INC |
| bool |
| default n |
| |
| config MMCONF_BASE_ADDRESS |
| hex |
| default 0xc0000000 |
| |
| config MMCONF_BUS_NUMBER |
| int |
| default 256 |
| |
| # TODO: Reservation for heap seems excessive |
| config HEAP_SIZE |
| hex |
| default 0xc0000 |
| |
| config RAMTOP |
| hex |
| default 0x400000 |
| |
| config BOOTBLOCK_NORTHBRIDGE_INIT |
| string |
| default "northbridge/amd/amdfam10/bootblock.c" |
| |
| config SB_HT_CHAIN_UNITID_OFFSET_ONLY |
| bool |
| default n |
| |
| config HT_CHAIN_DISTRIBUTE |
| def_bool n |
| |
| config DIMM_FBDIMM |
| bool |
| default n |
| |
| config DIMM_DDR2 |
| bool |
| default n |
| |
| config DIMM_DDR3 |
| bool |
| default n |
| |
| config DIMM_REGISTERED |
| bool |
| default n |
| |
| config DIMM_VOLTAGE_SET_SUPPORT |
| bool |
| default n |
| |
| if DIMM_FBDIMM |
| config DIMM_SUPPORT |
| hex |
| default 0x0110 |
| endif |
| |
| config S3_DATA_SIZE |
| int |
| default 16384 |
| depends on (HAVE_ACPI_RESUME) |
| |
| config S3_DATA_POS |
| hex |
| default 0x0 |
| depends on (HAVE_ACPI_RESUME) |
| |
| if DIMM_DDR2 |
| if DIMM_REGISTERED |
| config DIMM_SUPPORT |
| hex |
| default 0x0104 |
| endif |
| |
| if !DIMM_REGISTERED |
| config DIMM_SUPPORT |
| hex |
| default 0x0004 |
| endif |
| endif |
| |
| if DIMM_DDR3 |
| if DIMM_REGISTERED |
| config DIMM_SUPPORT |
| hex |
| default 0x0005 |
| endif |
| endif |
| |
| config SVI_HIGH_FREQ |
| bool |
| default n |
| help |
| Select this for boards with a Voltage Regulator able to operate |
| at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. |
| |
| menu "HyperTransport setup" |
| #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) |
| depends on (NORTHBRIDGE_AMD_AMDFAM10) |
| |
| choice |
| prompt "HyperTransport downlink width" |
| default LIMIT_HT_DOWN_WIDTH_16 |
| help |
| This option sets the maximum permissible HyperTransport |
| downlink width. |
| |
| Use of this option will only limit the autodetected HT width. |
| It will not (and cannot) increase the width beyond the autodetected |
| limits. |
| |
| This is primarily used to work around poorly designed or laid out HT |
| traces on certain motherboards. |
| |
| config LIMIT_HT_DOWN_WIDTH_8 |
| bool "8 bits" |
| config LIMIT_HT_DOWN_WIDTH_16 |
| bool "16 bits" |
| endchoice |
| |
| choice |
| prompt "HyperTransport uplink width" |
| default LIMIT_HT_UP_WIDTH_16 |
| help |
| This option sets the maximum permissible HyperTransport |
| uplink width. |
| |
| Use of this option will only limit the autodetected HT width. |
| It will not (and cannot) increase the width beyond the autodetected |
| limits. |
| |
| This is primarily used to work around poorly designed or laid out HT |
| traces on certain motherboards. |
| |
| config LIMIT_HT_UP_WIDTH_8 |
| bool "8 bits" |
| config LIMIT_HT_UP_WIDTH_16 |
| bool "16 bits" |
| endchoice |
| |
| endmenu |
| |
| endif # NORTHBRIDGE_AMD_AMDFAM10 |