Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
ce642f08b953dd752c5edeb1899b193c202d22fd
/
.
/
src
/
northbridge
/
intel
/
pineview
/
bootblock.c
blob: a67cc1aeb5d10aed9bfd6fce43bd7878c765f8c4 [
file
] [
log
] [
blame
]
#include
<arch/io.h>
#define
PCIEXBAR
0x60
#define
MMCONF_256_BUSSES
16
#define
ENABLE
1
static
void
bootblock_northbridge_init
(
void
)
{
pci_io_write_config32
(
PCI_DEV
(
0
,
0
,
0
),
PCIEXBAR
,
CONFIG_MMCONF_BASE_ADDRESS
|
MMCONF_256_BUSSES
|
ENABLE
);
}