| chip soc/intel/cannonlake |
| |
| # Enable Enhanced Intel SpeedStep |
| register "eist_enable" = "1" |
| |
| # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) |
| register "SaGv" = "SaGv_Enabled" |
| |
| # FSP Silicon (soc/intel/cannonlake/fsp_params.c) |
| |
| # Acoustic Noise |
| register "AcousticNoiseMitigation" = "1" |
| |
| register "FastPkgCRampDisableIa" = "1" |
| register "FastPkgCRampDisableGt" = "1" |
| register "FastPkgCRampDisableSa" = "1" |
| register "FastPkgCRampDisableFivr" = "1" |
| |
| register "SlowSlewRateForIa" = "3" # fast/16 |
| register "SlowSlewRateForGt" = "3" # fast/16 |
| register "SlowSlewRateForSa" = "3" # fast/16 |
| register "SlowSlewRateForFivr" = "3" # fast/16 |
| |
| # Power |
| register "PchPmSlpS3MinAssert" = "3" # 50ms |
| register "PchPmSlpS4MinAssert" = "1" # 1s |
| register "PchPmSlpSusMinAssert" = "2" # 500ms |
| register "PchPmSlpAMinAssert" = "4" # 2s |
| |
| # Thermal |
| register "tcc_offset" = "10" |
| |
| # PM Util (soc/intel/cannonlake/pmutil.c) |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route. i.e. If this route changes then the affected GPE |
| # offset bits also need to be changed. |
| # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) |
| register "gpe0_dw0" = "PMC_GPP_C" |
| register "gpe0_dw1" = "PMC_GPP_D" |
| register "gpe0_dw2" = "PMC_GPP_E" |
| |
| # Actual device tree |
| device cpu_cluster 0 on end |
| |
| device domain 0 on |
| device ref system_agent on end |
| device ref igpu on end |
| device ref dptf on |
| register "Device4Enable" = "1" |
| end |
| device ref thermal on end |
| device ref ish off end |
| device ref xhci on end |
| device ref xdci off end |
| device ref i2c0 off end |
| device ref i2c1 off end |
| device ref i2c2 off end |
| device ref i2c3 off end |
| device ref heci1 off end |
| device ref heci2 off end |
| device ref csme_ider off end |
| device ref csme_ktr off end |
| device ref heci3 off end |
| device ref heci4 off end |
| device ref sata on end |
| device ref i2c4 off end |
| device ref i2c5 off end |
| device ref uart2 off end |
| device ref emmc off end |
| device ref pcie_rp1 off end |
| device ref pcie_rp2 off end |
| device ref pcie_rp3 off end |
| device ref pcie_rp4 off end |
| device ref pcie_rp5 off end |
| device ref pcie_rp6 off end |
| device ref pcie_rp7 off end |
| device ref pcie_rp8 off end |
| device ref pcie_rp9 off end |
| device ref pcie_rp10 off end |
| device ref pcie_rp11 off end |
| device ref pcie_rp12 off end |
| device ref pcie_rp13 off end |
| device ref pcie_rp14 off end |
| device ref pcie_rp15 off end |
| device ref pcie_rp16 off end |
| device ref uart0 off end |
| device ref uart1 off end |
| device ref gspi0 off end |
| device ref gspi1 off end |
| device ref lpc_espi on end |
| device ref p2sb off end |
| device ref pmc hidden end |
| device ref hda on |
| register "PchHdaAudioLinkHda" = "1" |
| end |
| device ref smbus on end |
| device ref fast_spi on end |
| device ref gbe off end |
| end |
| end |