coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c
index 631adea..f013f69 100644
--- a/src/mainboard/intel/apollolake_rvp/romstage.c
+++ b/src/mainboard/intel/apollolake_rvp/romstage.c
@@ -122,7 +122,7 @@
mupd->FspmConfig.LowMemoryMaxValue = 0;
mupd->FspmConfig.HighMemoryMaxValue = 0;
- if (IS_ENABLED(CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1))
+ if (CONFIG(BOARD_INTEL_APOLLOLAKE_RVP1))
rvp1_fill_memory_params(mupd);
else
rvp2_fill_memory_params(mupd);
diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c
index c5293dc..af2101f 100644
--- a/src/mainboard/intel/baskingridge/acpi_tables.c
+++ b/src/mainboard/intel/baskingridge/acpi_tables.c
@@ -71,7 +71,7 @@
gnvs->tpmp = 1;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Emerald Lake has no EC (?) */
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif
diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c
index 9424855..3280878 100644
--- a/src/mainboard/intel/bayleybay_fsp/mainboard.c
+++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c
@@ -19,7 +19,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <arch/interrupt.h>
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c
index c34d82f..0b8c16b 100644
--- a/src/mainboard/intel/bayleybay_fsp/romstage.c
+++ b/src/mainboard/intel/bayleybay_fsp/romstage.c
@@ -163,7 +163,7 @@
UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig;
/* Disable 2nd DIMM on Bakersport*/
-#if IS_ENABLED(CONFIG_BOARD_INTEL_BAKERSPORT_FSP)
+#if CONFIG(BOARD_INTEL_BAKERSPORT_FSP)
UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */
#endif
}
diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c
index 946a453..88cfb1d 100644
--- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c
+++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c
@@ -19,7 +19,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <arch/interrupt.h>
diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
index 88b69da..c719d23 100644
--- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -39,7 +39,7 @@
}
}
- #if IS_ENABLED(CONFIG_CHROMEOS)
+ #if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
index 390929e..5ceff51 100644
--- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
+++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
@@ -44,7 +44,7 @@
const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
+ if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU))
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
else
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
@@ -57,7 +57,7 @@
const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
+ if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU))
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
else
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
index a1354da..2455422 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
@@ -163,7 +163,7 @@
/* D23 : SPP_MCLK */
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* E0 : SATAXPCIE_0_SATAGP_0 */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
+#if CONFIG(BOARD_INTEL_CANNONLAKE_RVPY)
PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),
#endif
/* E1 : SATAXPCIE_1_SATAGP_1 */
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
index f3be0e8..343b721 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
@@ -21,19 +21,19 @@
void __weak variant_nhlt_init(struct nhlt *nhlt)
{
/* 1-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
+ if (CONFIG(NHLT_DMIC_1CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 1))
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
/* 2-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
+ if (CONFIG(NHLT_DMIC_2CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 2))
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
/* 4-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
+ if (CONFIG(NHLT_DMIC_4CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT))
+ if (CONFIG(INCLUDE_SND_MAX98357_DA7219_NHLT))
{
/* Dialog for Headset codec.
* Headset codec is bi-directional but uses the same configuration
@@ -47,7 +47,7 @@
printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
}
- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) &&
+ if (CONFIG(INCLUDE_SND_MAX98373_NHLT) &&
!nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1))
printk(BIOS_ERR, "Added Maxim_98373 codec.\n");
}
diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl
index 2ccf3b7..70d0bd6 100644
--- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl
@@ -39,7 +39,7 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
index fc35050..b0091bd 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
@@ -17,7 +17,7 @@
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
-#if !IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
static const struct pad_config gpio_table[] = {
/* GPPC */
/* A0 : RCINB_TIME_SYNC_1 */
@@ -264,7 +264,7 @@
/* H21 : GPPC_H_21 */
/* H22 : GPPC_H_22 */
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
-#if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP)
+#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP)
PAD_CFG_GPO(GPP_H22, 1, PLTRST),
#else
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
index 161cc5f..34b161f 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
@@ -21,19 +21,19 @@
void __weak variant_nhlt_init(struct nhlt *nhlt)
{
/* 1-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
+ if (CONFIG(NHLT_DMIC_1CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 1))
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
/* 2-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
+ if (CONFIG(NHLT_DMIC_2CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 2))
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
/* 4-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
+ if (CONFIG(NHLT_DMIC_4CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)) {
+ if (CONFIG(INCLUDE_SND_MAX98357_DA7219_NHLT)) {
/* Dialog for Headset codec.
* Headset codec is bi-directional but uses the same
* configuration settings for render and capture endpoints.
@@ -46,7 +46,7 @@
printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
}
- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) &&
+ if (CONFIG(INCLUDE_SND_MAX98373_NHLT) &&
!nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1))
printk(BIOS_ERR, "Added Maxim_98373 codec.\n");
}
diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl
index 8adc853..20c71a3 100644
--- a/src/mainboard/intel/dcp847ske/acpi/superio.asl
+++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl
@@ -19,7 +19,7 @@
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x4e
-#if !IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS)
+#if !CONFIG(DISABLE_UART_ON_TESTPADS)
#define NCT6776_SHOW_SP1 1
#endif
#define NCT6776_SHOW_HWM 1
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 1a46f8b..5100735 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -27,7 +27,7 @@
#include "superio.h"
#include "thermal.h"
-#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS)
+#if CONFIG(DISABLE_UART_ON_TESTPADS)
#define DEBUG_UART_EN 0
#else
#define DEBUG_UART_EN COMA_LPC_EN
@@ -46,7 +46,7 @@
/* Disable devices */
RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
-#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if CONFIG(USE_NATIVE_RAMINIT)
/* Enable Gigabit Ethernet */
if (RCBA32(BUC) & PCH_DISABLE_GBE) {
RCBA32(BUC) &= ~PCH_DISABLE_GBE;
@@ -125,7 +125,7 @@
SUPERIO_INITVAL(0x1a, 0x02),
SUPERIO_INITVAL(0x1b, 0x6a),
SUPERIO_INITVAL(0x27, 0x80),
-#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS)
+#if CONFIG(DISABLE_UART_ON_TESTPADS)
SUPERIO_INITVAL(0x2a, 0x80),
#else
SUPERIO_INITVAL(0x2a, 0x00),
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index ad31bba..24ec912 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -18,13 +18,13 @@
#include <stdint.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
-#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if CONFIG(USE_NATIVE_RAMINIT)
#include <northbridge/intel/sandybridge/raminit_native.h>
#else
#include <northbridge/intel/sandybridge/raminit.h>
#endif
-#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if !CONFIG(USE_NATIVE_RAMINIT)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
struct pei_data pei_data_template = {
diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c
index 1791ee3..1fd7fce 100644
--- a/src/mainboard/intel/galileo/gpio.c
+++ b/src/mainboard/intel/galileo/gpio.c
@@ -25,15 +25,15 @@
const struct reg_script *script;
/* Initialize the GPIO controllers */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
script = gen2_gpio_init;
else
script = gen1_gpio_init;
reg_script_run(script);
/* Initialize the RXD and TXD paths for UART0 */
- if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) {
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(ENABLE_BUILTIN_HSUART0)) {
+ if (CONFIG(GALILEO_GEN2))
script = gen2_hsuart0;
else
script = (reg_legacy_gpio_read(
@@ -51,7 +51,7 @@
printk(BIOS_INFO, "Galileo I2C chip initialization\n");
/* Determine the correct script for the board */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
script = gen2_i2c_init;
else
/* Determine which I2C address is in use */
@@ -69,7 +69,7 @@
uint32_t value;
/* Determine the correct PCIe reset pin */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
pin_number = GEN2_PCI_RESET_RESUMEWELL_GPIO;
else
pin_number = GEN1_PCI_RESET_RESUMEWELL_GPIO;
diff --git a/src/mainboard/intel/galileo/mainboard.c b/src/mainboard/intel/galileo/mainboard.c
index 2a8ade7..0237916 100644
--- a/src/mainboard/intel/galileo/mainboard.c
+++ b/src/mainboard/intel/galileo/mainboard.c
@@ -18,7 +18,7 @@
/* Set the board version */
const char *smbios_mainboard_version(void)
{
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
return "Gen 2";
return "1.0";
}
diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c
index a5b74a0..b78ed1b 100644
--- a/src/mainboard/intel/galileo/vboot.c
+++ b/src/mainboard/intel/galileo/vboot.c
@@ -60,7 +60,7 @@
*/
/* Determine the correct script for the board */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
script = gen2_i2c_init;
else
/* Determine which I2C address is in use */
@@ -86,7 +86,7 @@
*/
/* Determine the correct script for the board */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
script = gen2_tpm_reset;
else
/* Determine which I2C address is in use */
diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c
index 9c5aa6d..0676eac 100644
--- a/src/mainboard/intel/glkrvp/boardid.c
+++ b/src/mainboard/intel/glkrvp/boardid.c
@@ -27,7 +27,7 @@
{
MAYBE_STATIC int id = -1;
if (id < 0) {
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
id = variant_board_id();
else {
if (send_ec_command(EC_FAB_ID_CMD) == 0)
diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c
index 0138a9c..44b7824 100644
--- a/src/mainboard/intel/glkrvp/ec.c
+++ b/src/mainboard/intel/glkrvp/ec.c
@@ -54,7 +54,7 @@
void mainboard_ec_init(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
if (ENV_RAMSTAGE)
ramstage_ec_init();
else if (ENV_BOOTBLOCK)
@@ -69,7 +69,7 @@
| LPC_IOE_LGE_200);
}
- if (IS_ENABLED(CONFIG_GLK_INTEL_EC)) {
+ if (CONFIG(GLK_INTEL_EC)) {
printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n");
outb(0xaa, 0x66);
printk(BIOS_INFO, "Hack to turn on the CPU fan\n");
diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c
index 8e13590..7811d06 100644
--- a/src/mainboard/intel/glkrvp/romstage.c
+++ b/src/mainboard/intel/glkrvp/romstage.c
@@ -211,7 +211,7 @@
{
uint8_t boardid;
- if (IS_ENABLED(CONFIG_IS_GLK_RVP_1))
+ if (CONFIG(IS_GLK_RVP_1))
boardid = BOARD_ID_GLK_RVP1_DDR4;
else
boardid = BOARD_ID_GLK_RVP2_LP4;
diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c
index f6d98e5..9af8993 100644
--- a/src/mainboard/intel/glkrvp/smihandler.c
+++ b/src/mainboard/intel/glkrvp/smihandler.c
@@ -25,7 +25,7 @@
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
if (gpi_status_get(sts, EC_SMI_GPI))
chromeec_smi_process_events();
}
@@ -38,14 +38,14 @@
pads = variant_sleep_gpio_table(&num);
gpio_configure_pads(pads, num);
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
@@ -53,6 +53,6 @@
void mainboard_smi_espi_handler(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_process_events();
}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
index 8df1dc4..69a0a91 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
@@ -21,7 +21,7 @@
{
MAYBE_STATIC uint32_t id = BOARD_ID_INIT;
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
if (id == BOARD_ID_INIT) {
if (google_chromeec_get_board_version(&id))
id = BOARD_ID_UNKNOWN;
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
index 03f2147..3cbb4bc 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
@@ -91,7 +91,7 @@
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPSS_UART2_RXD*/
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */
-#if IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)
+#if CONFIG(TPM_ON_FAST_SPI)
PAD_CFG_GPI_INT(GPIO_67, UP_20K, DEEP, LEVEL),/*SPI TPM Interrupt */
#endif
PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
index dc23abd..170e87c 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
@@ -22,7 +22,7 @@
* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
* which is North community
*/
-#if IS_ENABLED(CONFIG_SOC_ESPI)
+#if CONFIG(SOC_ESPI)
#define EC_SCI_GPI GPE0A_ESPI_SCI_STS
#else
#define EC_SCI_GPI GPE0_DW1_05
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
index 5433bd5..c35a292 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
@@ -21,15 +21,15 @@
void __weak variant_nhlt_init(struct nhlt *nhlt)
{
/* 1-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
+ if (CONFIG(NHLT_DMIC_1CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 1))
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
/* 2-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
+ if (CONFIG(NHLT_DMIC_2CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 2))
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
/* 4-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
+ if (CONFIG(NHLT_DMIC_4CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c
index e3a0a01..44fdc4f 100644
--- a/src/mainboard/intel/harcuvar/romstage.c
+++ b/src/mainboard/intel/harcuvar/romstage.c
@@ -22,7 +22,7 @@
#include <fsp/soc_binding.h>
#include <string.h>
-#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
+#if CONFIG(ENABLE_FSP_MEMORY_DOWN)
/*
* Define platform specific Memory Down Configure structure.
@@ -118,7 +118,7 @@
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
-#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
+#if CONFIG(ENABLE_FSP_MEMORY_DOWN)
uint8_t *spd_data_ptr = NULL;
/* Get SPD data pointer */
diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
index 49ae2e6..ef2e164 100644
--- a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
+++ b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
Scope (\_SB)
{
Device (PWRB)
diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c
index 6ac312a..b56f047 100644
--- a/src/mainboard/intel/icelake_rvp/board_id.c
+++ b/src/mainboard/intel/icelake_rvp/board_id.c
@@ -34,7 +34,7 @@
MAYBE_STATIC int id = -1;
if (id < 0) {
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
id = get_board_id_via_ext_ec();
else{
uint8_t buffer[2];
diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl
index 53feeb9..ad469fa 100644
--- a/src/mainboard/intel/icelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/icelake_rvp/dsdt.asl
@@ -43,12 +43,12 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl
index a9a61dd..efed4de 100644
--- a/src/mainboard/intel/kblrvp/acpi/ec.asl
+++ b/src/mainboard/intel/kblrvp/acpi/ec.asl
@@ -22,7 +22,7 @@
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Enable LID switch and provide wake pin for EC */
#define EC_ENABLE_LID_SWITCH
diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
index 544d695..531cd21 100644
--- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl
+++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
Scope (\_SB)
{
Device (PWRB)
diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c
index d48c9c2..101b04b 100644
--- a/src/mainboard/intel/kblrvp/chromeos.c
+++ b/src/mainboard/intel/kblrvp/chromeos.c
@@ -43,7 +43,7 @@
int get_lid_switch(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
/* Read lid switch state from the EC. */
return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
@@ -53,7 +53,7 @@
int get_recovery_mode_switch(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
/* Check for dedicated recovery switch first. */
if (google_chromeec_get_switches() &
EC_SWITCH_DEDICATED_RECOVERY)
@@ -70,7 +70,7 @@
int clear_recovery_mode_switch(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
/* Clear keyboard recovery event. */
return google_chromeec_clear_events_b(
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl
index ddb69da..8a16551 100644
--- a/src/mainboard/intel/kblrvp/dsdt.asl
+++ b/src/mainboard/intel/kblrvp/dsdt.asl
@@ -51,7 +51,7 @@
#include "acpi/ipu_mainboard.asl"
#include "acpi/mipi_camera.asl"
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/intel/kblrvp/hda_verb.c b/src/mainboard/intel/kblrvp/hda_verb.c
index bbe0af0..fdd196d 100644
--- a/src/mainboard/intel/kblrvp/hda_verb.c
+++ b/src/mainboard/intel/kblrvp/hda_verb.c
@@ -14,6 +14,6 @@
* GNU General Public License for more details.
*/
-#if !IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)
+#if !CONFIG(BOARD_INTEL_KBLRVP8)
#include "variant/hda_verb.h"
#endif
diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c
index 38279c3..604c069 100644
--- a/src/mainboard/intel/kblrvp/mainboard.c
+++ b/src/mainboard/intel/kblrvp/mainboard.c
@@ -27,7 +27,7 @@
static void mainboard_init(struct device *dev)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
mainboard_ec_init();
}
diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index 0b52f37..ad55c26 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -32,7 +32,7 @@
static void ioexpander_init(void *unused)
{
- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11))
+ if (CONFIG(BOARD_INTEL_KBLRVP11))
return;
printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n");
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c
index 8e5ffcf..c96f791 100644
--- a/src/mainboard/intel/kblrvp/romstage.c
+++ b/src/mainboard/intel/kblrvp/romstage.c
@@ -42,7 +42,7 @@
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) {
+ if (CONFIG(BOARD_INTEL_KBLRVP3)) {
struct region_device spd_rdev;
mem_cfg->DqPinsInterleaved = 0;
diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c
index bb09d78..ba8458b 100644
--- a/src/mainboard/intel/kblrvp/smihandler.c
+++ b/src/mainboard/intel/kblrvp/smihandler.c
@@ -47,25 +47,25 @@
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
{
- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))
+ if (CONFIG(BOARD_INTEL_KBLRVP8))
return;
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
if (gpi_status_get(sts, EC_SMI_GPI))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(u8 slp_typ)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c
index 64cc34b..df02601 100644
--- a/src/mainboard/intel/kunimitsu/smihandler.c
+++ b/src/mainboard/intel/kunimitsu/smihandler.c
@@ -54,14 +54,14 @@
void mainboard_smi_sleep(u8 slp_typ)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c
index efd20a5..9ff0639 100644
--- a/src/mainboard/intel/strago/ec.c
+++ b/src/mainboard/intel/strago/ec.c
@@ -33,7 +33,7 @@
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
post_code(0xf1);
diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c
index 6cd01e2..052e830 100644
--- a/src/mainboard/intel/strago/smihandler.c
+++ b/src/mainboard/intel/strago/smihandler.c
@@ -54,14 +54,14 @@
return 1;
}
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
@@ -88,7 +88,7 @@
*/
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
@@ -102,7 +102,7 @@
/* Disable USB charging if required */
switch (slp_typ) {
case ACPI_S3:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -117,7 +117,7 @@
enable_gpe(WAKE_GPIO_EN);
break;
case ACPI_S5:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -131,7 +131,7 @@
break;
}
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
@@ -150,7 +150,7 @@
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
@@ -159,7 +159,7 @@
#endif
break;
case APM_CNT_ACPI_DISABLE:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)