coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c
index d21b500..837cb13 100644
--- a/src/mainboard/advansus/a785e-i/get_bus_conf.c
+++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 92002a6..efc5913 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -138,7 +138,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -152,7 +152,7 @@
rs780_early_setup();
sb800_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index c805015..94897c8 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -83,18 +83,18 @@
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams_reset->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = FALSE;
FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio;
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM))
+ if (CONFIG(HUDSON_IMC_FWM))
oem_fan_control(FchParams_env);
/* XHCI configuration */
- if (IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE))
+ if (CONFIG(HUDSON_XHCI_ENABLE))
FchParams_env->Usb.Xhci0Enable = TRUE;
else
FchParams_env->Usb.Xhci0Enable = FALSE;
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index f250168..5201fa3 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -34,7 +34,7 @@
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
-#if IS_ENABLED(CONFIG_HUDSON_UART)
+#if CONFIG(HUDSON_UART)
configure_hudson_uart();
#endif
post_code(0x31);
diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
index 799455f6..df0a564 100644
--- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
@@ -36,7 +36,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 765bb24..e134ccd 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -131,7 +131,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -145,7 +145,7 @@
rs780_early_setup();
sb800_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
index 318d4a9..83db64c 100644
--- a/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
+++ b/src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c
@@ -135,7 +135,7 @@
LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
/* Enable IMC fan control. the recommended way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
FchParams->Hwm.HwMonitorEnable = TRUE;
FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */
@@ -272,7 +272,7 @@
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
- FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->FchReset.Xhci1Enable = FALSE;
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
@@ -293,7 +293,7 @@
oem_fan_control(FchParams);
/* XHCI configuration */
- FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE;
/* sata configuration */
diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c
index 89d66a5..6a4da62 100644
--- a/src/mainboard/amd/lamar/BiosCallOuts.c
+++ b/src/mainboard/amd/lamar/BiosCallOuts.c
@@ -150,7 +150,7 @@
LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
/* Enable IMC fan control. the recommended way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
@@ -287,7 +287,7 @@
FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- FchParams->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
/* Turn on FCH GPP slots */
FchParams->FchReset.GppEnable = TRUE;
diff --git a/src/mainboard/amd/lamar/OemCustomize.c b/src/mainboard/amd/lamar/OemCustomize.c
index 8cb7776..2cd013b 100644
--- a/src/mainboard/amd/lamar/OemCustomize.c
+++ b/src/mainboard/amd/lamar/OemCustomize.c
@@ -58,7 +58,7 @@
{ /* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */
DESCRIPTOR_TERMINATE_LIST,
PCIE_ENGINE_DATA_INITIALIZER(
- IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine,
+ CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine,
12, 15
),
PCIE_PORT_DATA_INITIALIZER_V2(
@@ -78,7 +78,7 @@
{ /* DP3 */
0,
PCIE_ENGINE_DATA_INITIALIZER(
- IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine,
+ CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine,
12, 15
),
PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux4, Hdp4)
diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
index ade9c79..cbf436b 100644
--- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 67b90a4..44f6b94 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -132,7 +132,7 @@
*/
wait_all_core0_started();
- #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+ #if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -146,7 +146,7 @@
rs780_early_setup();
sb7xx_51xx_early_setup();
- #if IS_ENABLED(CONFIG_SET_FIDVID)
+ #if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c
index 215309b..fa9f7c7 100644
--- a/src/mainboard/amd/olivehill/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehill/BiosCallOuts.c
@@ -102,7 +102,7 @@
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
diff --git a/src/mainboard/amd/olivehill/OemCustomize.c b/src/mainboard/amd/olivehill/OemCustomize.c
index 45dca01..df13fa5 100644
--- a/src/mainboard/amd/olivehill/OemCustomize.c
+++ b/src/mainboard/amd/olivehill/OemCustomize.c
@@ -101,7 +101,7 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}
diff --git a/src/mainboard/amd/olivehillplus/BiosCallOuts.c b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
index 3eea990..2f22f6c 100644
--- a/src/mainboard/amd/olivehillplus/BiosCallOuts.c
+++ b/src/mainboard/amd/olivehillplus/BiosCallOuts.c
@@ -118,7 +118,7 @@
LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
/* Enable IMC fan control. the recommended way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
FchParams->Hwm.HwMonitorEnable = TRUE;
FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */
@@ -256,7 +256,7 @@
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
- FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->FchReset.Xhci1Enable = FALSE;
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
@@ -270,7 +270,7 @@
oem_fan_control(FchParams);
/* XHCI configuration */
- FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE;
/* sata configuration */
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c
index 95b8e41..506a605 100644
--- a/src/mainboard/amd/parmer/BiosCallOuts.c
+++ b/src/mainboard/amd/parmer/BiosCallOuts.c
@@ -102,7 +102,7 @@
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
@@ -170,7 +170,7 @@
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{
- FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
}
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c
index 8375073..2eed8b2 100644
--- a/src/mainboard/amd/parmer/OemCustomize.c
+++ b/src/mainboard/amd/parmer/OemCustomize.c
@@ -166,7 +166,7 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c
index 7edc330..7ff6caa 100644
--- a/src/mainboard/amd/parmer/buildOpts.c
+++ b/src/mainboard/amd/parmer/buildOpts.c
@@ -152,7 +152,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
-#if IS_ENABLED(CONFIG_GFXUMA)
+#if CONFIG(GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index 0d4b344..61aa906 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -18,7 +18,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index d19ebda..e7421ce 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -235,7 +235,7 @@
*/
wait_all_core0_started();
- #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+ #if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -245,7 +245,7 @@
post_code(0x38);
- #if IS_ENABLED(CONFIG_SET_FIDVID)
+ #if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c
index 4fc97d0..249f301 100644
--- a/src/mainboard/amd/thatcher/BiosCallOuts.c
+++ b/src/mainboard/amd/thatcher/BiosCallOuts.c
@@ -102,7 +102,7 @@
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
@@ -171,7 +171,7 @@
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{
- FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
}
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c
index 9e383b4..96847a7 100644
--- a/src/mainboard/amd/thatcher/buildOpts.c
+++ b/src/mainboard/amd/thatcher/buildOpts.c
@@ -152,7 +152,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
-#if IS_ENABLED(CONFIG_GFXUMA)
+#if CONFIG(GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
index 0f30f16..6bdf94a 100644
--- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
@@ -46,7 +46,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index a90bac6..5b66f47 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -130,7 +130,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -144,7 +144,7 @@
rs780_early_setup();
sb7xx_51xx_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h
index f8f9d80..07567aa 100644
--- a/src/mainboard/amd/torpedo/Oem.h
+++ b/src/mainboard/amd/torpedo/Oem.h
@@ -16,7 +16,7 @@
#define BIOS_SIZE 0x04 //04 - 1MB
#endif
#define LEGACY_FREE 0x00
-#if !IS_ENABLED(CONFIG_ONBOARD_USB30)
+#if !CONFIG(ONBOARD_USB30)
#define XHCI_SUPPORT 0x01
#endif
diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
index 622fffe..557abec 100644
--- a/src/mainboard/amd/torpedo/platform_cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -294,7 +294,7 @@
#define INCHIP_USB_CINFIG 0x7F
#define INCHIP_USB_OHCI1_CINFIG 0x01
#define INCHIP_USB_OHCI2_CINFIG 0x01
-#if IS_ENABLED(CONFIG_ONBOARD_USB30)
+#if CONFIG(ONBOARD_USB30)
#define INCHIP_USB_OHCI3_CINFIG 0x00
#else
#define INCHIP_USB_OHCI3_CINFIG 0x01
@@ -962,7 +962,7 @@
* @li <b>0</b> - Disable
* @li <b>1</b> - Enable
*/
-#if IS_ENABLED(CONFIG_ONBOARD_USB30)
+#if CONFIG(ONBOARD_USB30)
#define SB_XHCI_SWITCH 0
#else
#define SB_XHCI_SWITCH 1
diff --git a/src/mainboard/apple/macbook21/gpio.c b/src/mainboard/apple/macbook21/gpio.c
index 19296a7..3ce6cf3 100644
--- a/src/mainboard/apple/macbook21/gpio.c
+++ b/src/mainboard/apple/macbook21/gpio.c
@@ -56,8 +56,8 @@
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
-#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \
- IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21)
+#if CONFIG(BOARD_APPLE_MACBOOK11) || \
+ CONFIG(BOARD_APPLE_MACBOOK21)
.gpio5 = GPIO_LEVEL_LOW,
#else /* CONFIG_BOARD_APPLE_IMAC52 */
.gpio5 = GPIO_LEVEL_HIGH,
@@ -72,8 +72,8 @@
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio1 = GPIO_INVERT,
.gpio7 = GPIO_INVERT,
-#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \
- IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21)
+#if CONFIG(BOARD_APPLE_MACBOOK11) || \
+ CONFIG(BOARD_APPLE_MACBOOK21)
.gpio13 = GPIO_INVERT,
#endif
};
@@ -82,7 +82,7 @@
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52)
+#if CONFIG(BOARD_APPLE_IMAC52)
.gpio35 = GPIO_MODE_GPIO,
#endif
.gpio38 = GPIO_MODE_GPIO,
@@ -91,7 +91,7 @@
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52)
+#if CONFIG(BOARD_APPLE_IMAC52)
.gpio35 = GPIO_DIR_OUTPUT,
#endif
.gpio38 = GPIO_DIR_OUTPUT,
@@ -100,7 +100,7 @@
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
-#if IS_ENABLED(CONFIG_BOARD_APPLE_IMAC52)
+#if CONFIG(BOARD_APPLE_IMAC52)
.gpio35 = GPIO_LEVEL_LOW,
#endif
.gpio38 = GPIO_LEVEL_HIGH,
diff --git a/src/mainboard/apple/macbook21/hda_verb.c b/src/mainboard/apple/macbook21/hda_verb.c
index 9ae5cf8..09d5f1a 100644
--- a/src/mainboard/apple/macbook21/hda_verb.c
+++ b/src/mainboard/apple/macbook21/hda_verb.c
@@ -19,8 +19,8 @@
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */
-#if IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK11) || \
- IS_ENABLED(CONFIG_BOARD_APPLE_MACBOOK21)
+#if CONFIG(BOARD_APPLE_MACBOOK11) || \
+ CONFIG(BOARD_APPLE_MACBOOK21)
0x106b2200, /* Subsystem ID */
0x0000000B, /* Number of 4 dword sets */
diff --git a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
index 09d961d..9687099 100644
--- a/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
+++ b/src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
@@ -18,7 +18,7 @@
* IRQ routing for the 0:1e.0 PCI bridge of the ICH7
*/
-#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_VS3_R2_0)
+#if CONFIG(BOARD_ASROCK_G41M_VS3_R2_0)
If (PICM) {
Return (Package() {
/* PCI1 SLOT 1 */
@@ -53,9 +53,9 @@
})
}
#else
-/* IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0) \
- || IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS) \
- || IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS) */
+/* CONFIG(BOARD_ASROCK_G41C_GS_R2_0) \
+ || CONFIG(BOARD_ASROCK_G41C_GS) \
+ || CONFIG(BOARD_ASROCK_G41M_GS) */
If (PICM) {
Return (Package() {
/* PCI1 SLOT 1 */
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index 8474d18..8cf3487 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -44,7 +44,7 @@
setup_pch_gpios(&mainboard_gpio_map);
/* Set GPIOs on superio, enable UART */
- if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) {
+ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) {
nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);
pnp_set_logical_device(SERIAL_DEV_R2);
diff --git a/src/mainboard/asrock/imb-a180/OemCustomize.c b/src/mainboard/asrock/imb-a180/OemCustomize.c
index 3b1c903..eaa27b7 100644
--- a/src/mainboard/asrock/imb-a180/OemCustomize.c
+++ b/src/mainboard/asrock/imb-a180/OemCustomize.c
@@ -102,7 +102,7 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}
diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c
index c8cc68a..c01ea74 100644
--- a/src/mainboard/asus/am1i-a/BiosCallOuts.c
+++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c
@@ -99,7 +99,7 @@
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{
- FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams_reset->Mode = 6;
/* Read SATA speed setting from CMOS */
diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c
index f1bf60e..e001d43 100644
--- a/src/mainboard/asus/am1i-a/OemCustomize.c
+++ b/src/mainboard/asus/am1i-a/OemCustomize.c
@@ -104,8 +104,8 @@
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
- FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->SataEnable = 1;
FchReset->IdeEnable = 0;
diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
index 45e174c..9e60ca7 100644
--- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c
+++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
@@ -39,7 +39,7 @@
* Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
* the vendor BIOS.
*/
-#if !IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)
+#if !CONFIG(BOARD_ASUS_F2A85_M_LE)
const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
{0x11, 0x99430140},
{0x12, 0x411111f0},
@@ -85,7 +85,7 @@
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{
- FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
}
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index 9d96753..ec79fc8 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -134,8 +134,8 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
- FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
}
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
@@ -179,9 +179,9 @@
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
{
- if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M) || IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO))
+ if (CONFIG(BOARD_ASUS_F2A85_M) || CONFIG(BOARD_ASUS_F2A85_M_PRO))
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M;
- else if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE))
+ else if (CONFIG(BOARD_ASUS_F2A85_M_LE))
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M_LE;
}
diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl
index af8532f..c0aef87 100644
--- a/src/mainboard/asus/f2a85-m/acpi/routing.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl
@@ -46,7 +46,7 @@
/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
+#if CONFIG(BOARD_ASUS_F2A85_M_PRO)
Package(){0x000FFFFF, 0, INTA, 0 },
Package(){0x000FFFFF, 1, INTB, 0 },
Package(){0x000FFFFF, 2, INTC, 0 },
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index e69564e..dc20dc7 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -167,7 +167,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
-#if IS_ENABLED(CONFIG_GFXUMA)
+#if CONFIG(GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index bed5a73..dffb726 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -70,9 +70,9 @@
u8 byte;
pci_devfn_t dev;
- if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ if (CONFIG(POST_DEVICE_PCI_PCIE))
hudson_pci_port80();
- else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ else if (CONFIG(POST_DEVICE_LPC))
hudson_lpc_port80();
/* enable SIO LPC decode */
@@ -95,7 +95,7 @@
/* enable SIO clock */
sbxxx_enable_48mhzout();
- if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO))
+ if (CONFIG(BOARD_ASUS_F2A85_M_PRO))
superio_init_m_pro();
else
superio_init_m();
diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c
index 52840ca..d705b21 100644
--- a/src/mainboard/asus/kcma-d8/acpi_tables.c
+++ b/src/mainboard/asus/kcma-d8/acpi_tables.c
@@ -31,7 +31,7 @@
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
- if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+ if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
apicid_sp5100 = 0x0;
else
apicid_sp5100 = 0x20;
@@ -70,7 +70,7 @@
uint32_t apicid_sp5100;
uint32_t apicid_sr5650;
- if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+ if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
apicid_sp5100 = 0x0;
else
apicid_sp5100 = 0x20;
diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c
index 6cfc93c..543ffed 100644
--- a/src/mainboard/asus/kcma-d8/bootblock.c
+++ b/src/mainboard/asus/kcma-d8/bootblock.c
@@ -33,7 +33,7 @@
pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
if (recovery_enabled) {
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
+#if CONFIG(USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);
diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c
index 1abca65..c9b83a0 100644
--- a/src/mainboard/asus/kcma-d8/mptable.c
+++ b/src/mainboard/asus/kcma-d8/mptable.c
@@ -36,7 +36,7 @@
smp_write_processors(mc);
- if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+ if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
apicid_sp5100 = 0x0;
else
apicid_sp5100 = 0x20;
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 028af4c..a74c6dd 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -464,7 +464,7 @@
sr5650_early_setup();
sb7xx_51xx_early_setup();
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+ if (CONFIG(LOGICAL_CPUS)) {
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -472,7 +472,7 @@
wait_all_other_cores_started(bsp_apicid);
}
- if (IS_ENABLED(CONFIG_SET_FIDVID)) {
+ if (CONFIG(SET_FIDVID)) {
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
@@ -481,7 +481,7 @@
post_code(0x39);
- #if IS_ENABLED(CONFIG_SET_FIDVID)
+ #if CONFIG(SET_FIDVID)
if (!warm_reset_detect(0)) { // BSP is node 0
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
@@ -526,7 +526,7 @@
post_code(0x3B);
/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
wait_all_other_cores_stopped(bsp_apicid);
/* It's the time to set ctrl in sysinfo now; */
@@ -540,9 +540,9 @@
#if 0
/* FIXME
* After the AMD K10 code has been converted to use
- * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
+ * CONFIG(DEBUG_SMBUS) uncomment this block
*/
- if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
+ if (CONFIG(DEBUG_SMBUS)) {
dump_spd_registers(&cpu[0]);
dump_smbus_registers();
}
diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c
index ce3d417..587e2ff 100644
--- a/src/mainboard/asus/kfsn4-dre/acpi_tables.c
+++ b/src/mainboard/asus/kfsn4-dre/acpi_tables.c
@@ -48,7 +48,7 @@
CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
/* Initialize interrupt mapping if mptable.c didn't. */
- if (!IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) {
+ if (!CONFIG(GENERATE_MP_TABLE)) {
/* Copied from mptable.c */
/* Enable interrupts for commonly used devices (USB, SATA, etc.) */
pci_write_config32(dev, 0x7c, 0x0d800018);
diff --git a/src/mainboard/asus/kfsn4-dre/bootblock.c b/src/mainboard/asus/kfsn4-dre/bootblock.c
index 796ca1a..fd57538 100644
--- a/src/mainboard/asus/kfsn4-dre/bootblock.c
+++ b/src/mainboard/asus/kfsn4-dre/bootblock.c
@@ -64,7 +64,7 @@
recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);
if (recovery_enabled) {
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
+#if CONFIG(USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);
diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
index 82172e8..bb51ada 100644
--- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
+++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
@@ -74,7 +74,7 @@
}
}
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+ if (CONFIG(LOGICAL_CPUS)) {
apicid_base = get_apicid_base(1);
printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base);
}
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index f6faf17..6ac33f2 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -251,7 +251,7 @@
*/
wait_all_core0_started();
- if (IS_ENABLED(CONFIG_SET_FIDVID)) {
+ if (CONFIG(SET_FIDVID)) {
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
@@ -270,7 +270,7 @@
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
}
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+ if (CONFIG(LOGICAL_CPUS)) {
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -311,9 +311,9 @@
#if 0
/* FIXME
* After the AMD K10 code has been converted to use
- * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
+ * CONFIG(DEBUG_SMBUS) uncomment this block
*/
- if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
+ if (CONFIG(DEBUG_SMBUS)) {
dump_spd_registers(&cpu[0]);
dump_smbus_registers();
}
diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c
index 52840ca..d705b21 100644
--- a/src/mainboard/asus/kgpe-d16/acpi_tables.c
+++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c
@@ -31,7 +31,7 @@
/* create all subtables for processors */
current = acpi_create_madt_lapics(current);
- if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+ if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
apicid_sp5100 = 0x0;
else
apicid_sp5100 = 0x20;
@@ -70,7 +70,7 @@
uint32_t apicid_sp5100;
uint32_t apicid_sr5650;
- if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+ if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
apicid_sp5100 = 0x0;
else
apicid_sp5100 = 0x20;
diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c
index 6cfc93c..543ffed 100644
--- a/src/mainboard/asus/kgpe-d16/bootblock.c
+++ b/src/mainboard/asus/kgpe-d16/bootblock.c
@@ -33,7 +33,7 @@
pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
if (recovery_enabled) {
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
+#if CONFIG(USE_OPTION_TABLE)
/* Clear NVRAM checksum */
for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
cmos_write(0x0, addr);
diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c
index 15d0f50..ed01b54 100644
--- a/src/mainboard/asus/kgpe-d16/mptable.c
+++ b/src/mainboard/asus/kgpe-d16/mptable.c
@@ -36,7 +36,7 @@
smp_write_processors(mc);
- if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+ if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
apicid_sp5100 = 0x0;
else
apicid_sp5100 = 0x20;
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 7e82347..7fe9b64 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -575,7 +575,7 @@
sr5650_early_setup();
sb7xx_51xx_early_setup();
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+ if (CONFIG(LOGICAL_CPUS)) {
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -583,7 +583,7 @@
wait_all_other_cores_started(bsp_apicid);
}
- if (IS_ENABLED(CONFIG_SET_FIDVID)) {
+ if (CONFIG(SET_FIDVID)) {
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
@@ -592,7 +592,7 @@
post_code(0x39);
- #if IS_ENABLED(CONFIG_SET_FIDVID)
+ #if CONFIG(SET_FIDVID)
if (!warm_reset_detect(0)) { // BSP is node 0
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
@@ -637,7 +637,7 @@
post_code(0x3B);
/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
wait_all_other_cores_stopped(bsp_apicid);
/* It's the time to set ctrl in sysinfo now; */
@@ -651,9 +651,9 @@
#if 0
/* FIXME
* After the AMD K10 code has been converted to use
- * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
+ * CONFIG(DEBUG_SMBUS) uncomment this block
*/
- if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
+ if (CONFIG(DEBUG_SMBUS)) {
dump_spd_registers(&cpu[0]);
dump_smbus_registers();
}
diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c
index ade9c79..cbf436b 100644
--- a/src/mainboard/asus/m4a78-em/get_bus_conf.c
+++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index ffe283c..08ca715 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -133,7 +133,7 @@
*/
wait_all_core0_started();
- #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+ #if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -147,7 +147,7 @@
rs780_early_setup();
sb7xx_51xx_early_setup();
- #if IS_ENABLED(CONFIG_SET_FIDVID)
+ #if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c
index ade9c79..cbf436b 100644
--- a/src/mainboard/asus/m4a785-m/get_bus_conf.c
+++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 3246bdd7..a53dbec 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -133,7 +133,7 @@
*/
wait_all_core0_started();
- #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+ #if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -147,7 +147,7 @@
rs780_early_setup();
sb7xx_51xx_early_setup();
- #if IS_ENABLED(CONFIG_SET_FIDVID)
+ #if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
@@ -218,7 +218,7 @@
*/
BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
{
-#if !IS_ENABLED(CONFIG_BOARD_ASUS_M4A785TM)
+#if !CONFIG(BOARD_ASUS_M4A785TM)
static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
/* If the BUID was adjusted in early_ht we need to do the manual override */
if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c
index d21b500..837cb13 100644
--- a/src/mainboard/asus/m5a88-v/get_bus_conf.c
+++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 899814f..42e5c12 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -138,7 +138,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -152,7 +152,7 @@
rs780_early_setup();
sb800_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index c59f38c..6295a53 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -76,7 +76,7 @@
pnp_enter_ext_func_mode(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV);
- if (IS_ENABLED(CONFIG_BOARD_ASUS_P5QPL_AM)) {
+ if (CONFIG(BOARD_ASUS_P5QPL_AM)) {
/*
* P5QPL-AM:
* BSEL0 -> not hooked up (not supported anyways)
diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c
index d21b500..837cb13 100644
--- a/src/mainboard/avalue/eax-785e/get_bus_conf.c
+++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index f415038..068fc06 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -138,7 +138,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -152,7 +152,7 @@
rs780_early_setup();
sb800_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
index 2cfe279..747b202 100644
--- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
@@ -105,7 +105,7 @@
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
@@ -195,7 +195,7 @@
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
u8 index;
- if (IS_ENABLED(CONFIG_BAP_E20_DDR3_1066))
+ if (CONFIG(BAP_E20_DDR3_1066))
index = 1;
else /* CONFIG_BAP_E20_DDR3_800 */
index = 0;
diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c
index 8b1fec0..29d01d6 100644
--- a/src/mainboard/bap/ode_e20XX/OemCustomize.c
+++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c
@@ -87,7 +87,7 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}
diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
index 3108dca..18e5b7c 100644
--- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c
@@ -120,7 +120,7 @@
LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
/* Enable IMC fan control. the recommended way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
FchParams->Hwm.HwMonitorEnable = TRUE;
FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 0 disable, 1 enable TSI Auto Polling */
@@ -258,7 +258,7 @@
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
- FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->FchReset.Xhci1Enable = FALSE;
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
@@ -272,7 +272,7 @@
oem_fan_control(FchParams);
/* XHCI configuration */
- FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE;
/* sata configuration */
@@ -303,9 +303,9 @@
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
u8 index;
- if (IS_ENABLED(CONFIG_BAP_E21_DDR3_1066))
+ if (CONFIG(BAP_E21_DDR3_1066))
index = 1;
- else if (IS_ENABLED(CONFIG_BAP_E21_DDR3_1333))
+ else if (CONFIG(BAP_E21_DDR3_1333))
index = 2;
else /* CONFIG_BAP_E21_DDR3_800 */
index = 0;
diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
index d1036ab..7044797 100644
--- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
+++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c
@@ -102,7 +102,7 @@
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
diff --git a/src/mainboard/biostar/a68n_5200/OemCustomize.c b/src/mainboard/biostar/a68n_5200/OemCustomize.c
index 45dca01..df13fa5 100644
--- a/src/mainboard/biostar/a68n_5200/OemCustomize.c
+++ b/src/mainboard/biostar/a68n_5200/OemCustomize.c
@@ -101,7 +101,7 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}
diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c
index 15834fb..e188808 100644
--- a/src/mainboard/biostar/a68n_5200/romstage.c
+++ b/src/mainboard/biostar/a68n_5200/romstage.c
@@ -60,10 +60,10 @@
pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
pci_write_config32(dev, 0x44, 0xff03ffd5);
- if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ if (CONFIG(POST_DEVICE_PCI_PCIE))
hudson_pci_port80();
- if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ if (CONFIG(POST_DEVICE_LPC))
hudson_lpc_port80();
/* enable SIO LPC decode */
diff --git a/src/mainboard/biostar/am1ml/BiosCallOuts.c b/src/mainboard/biostar/am1ml/BiosCallOuts.c
index 7095140..0390cea 100644
--- a/src/mainboard/biostar/am1ml/BiosCallOuts.c
+++ b/src/mainboard/biostar/am1ml/BiosCallOuts.c
@@ -94,7 +94,7 @@
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{
- FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
FchParams_reset->Mode = 6;
}
diff --git a/src/mainboard/biostar/am1ml/OemCustomize.c b/src/mainboard/biostar/am1ml/OemCustomize.c
index 6802df7..2f7666e 100644
--- a/src/mainboard/biostar/am1ml/OemCustomize.c
+++ b/src/mainboard/biostar/am1ml/OemCustomize.c
@@ -103,8 +103,8 @@
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
- FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->SataEnable = 1;
FchReset->IdeEnable = 0;
diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c
index a13b966..ad758c9 100644
--- a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c
+++ b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c
@@ -20,7 +20,7 @@
void bootblock_mainboard_early_init(void)
{
- if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ if (CONFIG(BOOTBLOCK_CONSOLE)) {
if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE))
uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD);
}
diff --git a/src/mainboard/compulab/intense_pc/gpio.c b/src/mainboard/compulab/intense_pc/gpio.c
index 373c9f1..dc98da8 100644
--- a/src/mainboard/compulab/intense_pc/gpio.c
+++ b/src/mainboard/compulab/intense_pc/gpio.c
@@ -74,7 +74,7 @@
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
- #if IS_ENABLED(CONFIG_ENABLE_MSATA)
+ #if CONFIG(ENABLE_MSATA)
.gpio8 = GPIO_LEVEL_LOW,
#else
.gpio8 = GPIO_LEVEL_HIGH,
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c
index 3cb7067..dbd28c8 100644
--- a/src/mainboard/compulab/intense_pc/romstage.c
+++ b/src/mainboard/compulab/intense_pc/romstage.c
@@ -38,7 +38,7 @@
/* Map a range for the runtime_port registers to the LPC bus. */
pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
+#if CONFIG(DRIVERS_UART_8250IO)
/* Enable COM1 */
if (sio1007_enable_uart_at(SIO_PORT)) {
pci_write_config16(dev, LPC_EN,
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 1493565d..852800d 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -166,7 +166,7 @@
IORESOURCE_ASSIGNED;
}
-#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
+#if CONFIG(GENERATE_SMBIOS_TABLES)
static int qemu_get_smbios_data16(int handle, unsigned long *current)
{
struct smbios_type16 *t = (struct smbios_type16 *)*current;
@@ -229,7 +229,7 @@
.enable_resources = NULL,
.init = NULL,
.scan_bus = pci_domain_scan_bus,
-#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
+#if CONFIG(GENERATE_SMBIOS_TABLES)
.get_smbios_data = qemu_get_smbios_data,
#endif
};
diff --git a/src/mainboard/emulation/qemu-power8/bootblock.c b/src/mainboard/emulation/qemu-power8/bootblock.c
index 5cfb7c1..bf918cf 100644
--- a/src/mainboard/emulation/qemu-power8/bootblock.c
+++ b/src/mainboard/emulation/qemu-power8/bootblock.c
@@ -22,7 +22,7 @@
*/
void main(void)
{
- if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ if (CONFIG(BOOTBLOCK_CONSOLE)) {
console_init();
}
diff --git a/src/mainboard/foxconn/g41s-k/acpi/superio.asl b/src/mainboard/foxconn/g41s-k/acpi/superio.asl
index 9432aca..6247011 100644
--- a/src/mainboard/foxconn/g41s-k/acpi/superio.asl
+++ b/src/mainboard/foxconn/g41s-k/acpi/superio.asl
@@ -26,14 +26,14 @@
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x2e
#define IT8720F_SHOW_SP1 1
-#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
+#if CONFIG(BOARD_FOXCONN_G41S_K)
#define IT8720F_SHOW_SP2 1
#endif
#define IT8720F_SHOW_EC 1
#define IT8720F_SHOW_KBCK 1
#define IT8720F_SHOW_KBCM 1
#define IT8720F_SHOW_GPIO 1
-#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
+#if CONFIG(BOARD_FOXCONN_G41S_K)
#define IT8720F_SHOW_CIR 1
#endif
#include <superio/ite/it8720f/acpi/superio.asl>
diff --git a/src/mainboard/foxconn/g41s-k/hda_verb.c b/src/mainboard/foxconn/g41s-k/hda_verb.c
index 9ac3c3b..bb787b2 100644
--- a/src/mainboard/foxconn/g41s-k/hda_verb.c
+++ b/src/mainboard/foxconn/g41s-k/hda_verb.c
@@ -17,7 +17,7 @@
#include <device/azalia_device.h>
-#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
+#if CONFIG(BOARD_FOXCONN_G41S_K)
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0888, /* Vendor ID */
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index e6301df..47a7d40 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -82,7 +82,7 @@
void mainboard_romstage_entry(unsigned long bist)
{
// ch0 ch1
-#if IS_ENABLED(CONFIG_BOARD_FOXCONN_G41S_K)
+#if CONFIG(BOARD_FOXCONN_G41S_K)
const u8 spd_addrmap[4] = { 0x50, 0, 0, 0 };
#else
/* TODO adapt raminit such that other slots can be used
diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
index ade9c79..cbf436b 100644
--- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 63a4509..319417c 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -132,7 +132,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -146,7 +146,7 @@
rs780_early_setup();
sb7xx_51xx_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
index 0de0760..241e187 100644
--- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 497acaa..c98b632 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -132,7 +132,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -146,7 +146,7 @@
rs780_early_setup();
sb7xx_51xx_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
index ade9c79..cbf436b 100644
--- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index a974422..d78564d 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -133,7 +133,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -147,7 +147,7 @@
rs780_early_setup();
sb7xx_51xx_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
index 8efe2df..0c2c81f 100644
--- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
+++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
@@ -102,7 +102,7 @@
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
diff --git a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
index b98b2ac..6b21f0c 100644
--- a/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
+++ b/src/mainboard/gizmosphere/gizmo2/OemCustomize.c
@@ -95,7 +95,7 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}
diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl
index 204c1c4..a07ce3e 100644
--- a/src/mainboard/google/auron/acpi/mainboard.asl
+++ b/src/mainboard/google/auron/acpi/mainboard.asl
@@ -16,7 +16,7 @@
#include <variant/onboard.h>
-#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_BUDDY)
+#if !CONFIG(BOARD_GOOGLE_BUDDY)
Scope (\_SB.PCI0.RP01)
{
Device (WLAN)
diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c
index 247fc2f..790eeff 100644
--- a/src/mainboard/google/auron/smihandler.c
+++ b/src/mainboard/google/auron/smihandler.c
@@ -33,7 +33,7 @@
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
@@ -65,7 +65,7 @@
static void mainboard_disable_gpios(void)
{
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_SAMUS)
+#if CONFIG(BOARD_GOOGLE_SAMUS)
/* Put SSD in reset to prevent leak */
set_gpio(BOARD_SSD_RESET_GPIO, 0);
/* Disable LTE */
diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c
index d072fd9..5afb26c 100644
--- a/src/mainboard/google/auron/variants/buddy/variant.c
+++ b/src/mainboard/google/auron/variants/buddy/variant.c
@@ -131,7 +131,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c
index f7b51a9..4da0a2b 100644
--- a/src/mainboard/google/beltino/acpi_tables.c
+++ b/src/mainboard/google/beltino/acpi_tables.c
@@ -69,7 +69,7 @@
gnvs->tpmp = 1;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// SuperIO is always RO
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif
diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c
index 1d0bc43..7286437 100644
--- a/src/mainboard/google/beltino/lan.c
+++ b/src/mainboard/google/beltino/lan.c
@@ -115,7 +115,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index 993c5e8..6b69277 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -188,7 +188,7 @@
struct device *ethernet_dev = NULL;
void *vpd_file;
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 9f98c8b..726e561 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -26,7 +26,7 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <halt.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#endif
diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl
index dd6bb68..70ab862 100644
--- a/src/mainboard/google/cyan/acpi/dptf.asl
+++ b/src/mainboard/google/cyan/acpi/dptf.asl
@@ -21,6 +21,6 @@
#include <variant/acpi/dptf.asl>
/* Include SoC DPTF */
-#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA)
+#if !CONFIG(BOARD_GOOGLE_TERRA)
#include <acpi/dptf/dptf.asl>
#endif
diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c
index e7c91d2..0db5824 100644
--- a/src/mainboard/google/cyan/acpi_tables.c
+++ b/src/mainboard/google/cyan/acpi_tables.c
@@ -35,7 +35,7 @@
gnvs->dpte = 1;
/* Disable PMIC I2C port for ACPI for all boards except cyan */
- if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN))
+ if (!CONFIG(BOARD_GOOGLE_CYAN))
gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
}
diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c
index 752637c..4b148f8 100644
--- a/src/mainboard/google/cyan/chromeos.c
+++ b/src/mainboard/google/cyan/chromeos.c
@@ -54,7 +54,7 @@
* in the reading.
*/
#if ENV_ROMSTAGE
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+ if (CONFIG(BOARD_GOOGLE_CYAN)) {
write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0),
(PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));
write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1),
@@ -65,7 +65,7 @@
#endif
/* WP is enabled when the pin is reading high. */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+ if (CONFIG(BOARD_GOOGLE_CYAN)) {
return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0))
& PAD_VAL_HIGH);
} else {
diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl
index 13b83b7..397f6d2 100644
--- a/src/mainboard/google/cyan/dsdt.asl
+++ b/src/mainboard/google/cyan/dsdt.asl
@@ -37,7 +37,7 @@
Device (PCI0)
{
#include <acpi/southcluster.asl>
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA)
+#if CONFIG(BOARD_GOOGLE_TERRA)
#include <variant/acpi/cpu.asl>
#else
#include <acpi/dptf/cpu.asl>
diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c
index efd20a5..9ff0639 100644
--- a/src/mainboard/google/cyan/ec.c
+++ b/src/mainboard/google/cyan/ec.c
@@ -33,7 +33,7 @@
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
post_code(0xf1);
diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c
index ef0f489..aa20593 100644
--- a/src/mainboard/google/cyan/romstage.c
+++ b/src/mainboard/google/cyan/romstage.c
@@ -33,7 +33,7 @@
MEMORY_INIT_UPD *memory_params)
{
/* Update SPD data */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+ if (CONFIG(BOARD_GOOGLE_CYAN)) {
memory_params->PcdMemoryTypeEnable = MEM_DDR3;
memory_params->PcdMemorySpdPtr =
(u32)params->pei_data->spd_data_ch0;
diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c
index 88400f7..852d9c9 100644
--- a/src/mainboard/google/cyan/smihandler.c
+++ b/src/mainboard/google/cyan/smihandler.c
@@ -55,14 +55,14 @@
return 1;
}
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
@@ -89,7 +89,7 @@
*/
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
@@ -106,7 +106,7 @@
/* Disable USB charging if required */
switch (slp_typ) {
case ACPI_S3:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -121,7 +121,7 @@
enable_gpe(WAKE_GPIO_EN);
break;
case ACPI_S5:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -145,7 +145,7 @@
break;
}
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
@@ -165,7 +165,7 @@
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
@@ -174,7 +174,7 @@
#endif
break;
case APM_CNT_ACPI_DISABLE:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index b7b0c30..af694a4 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -81,7 +81,7 @@
spd_content = get_spd_pointer(spd_file,
spd_file_len / SPD_PAGE_LEN,
&dual_channel);
- if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) {
+ if (CONFIG(DISPLAY_SPD_DATA) && spd_content != NULL) {
printk(BIOS_DEBUG, "SPD Data:\n");
hexdump(spd_content, SPD_PAGE_LEN);
printk(BIOS_DEBUG, "\n");
@@ -137,7 +137,7 @@
}
/* Parse the SPD data to determine the DIMM information */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+ if (CONFIG(BOARD_GOOGLE_CYAN)) {
dimm->ddr_type = MEMORY_TYPE_DDR3;
} else {
dimm->ddr_type = MEMORY_TYPE_LPDDR3;
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl
index 2e9ce63..ab0b977 100644
--- a/src/mainboard/google/dragonegg/dsdt.asl
+++ b/src/mainboard/google/dragonegg/dsdt.asl
@@ -43,7 +43,7 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c
index b4cb332..4cf2a85 100644
--- a/src/mainboard/google/foster/chromeos.c
+++ b/src/mainboard/google/foster/chromeos.c
@@ -68,7 +68,7 @@
int get_recovery_mode_switch(void)
{
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
uint64_t ec_events;
ec_events = google_chromeec_get_events_b();
diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c
index 9e1a0f3..5684f8f 100644
--- a/src/mainboard/google/gale/mainboard.c
+++ b/src/mainboard/google/gale/mainboard.c
@@ -46,7 +46,7 @@
setup_mmu(DRAM_INITIALIZED);
setup_usb();
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
/* Copy WIFI calibration data into CBMEM. */
cbmem_add_vpd_calibration_data();
}
@@ -80,7 +80,7 @@
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = REGION_SIZE(dma_coherent);
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
}
diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c
index 1a3f5a4..1edd8a7 100644
--- a/src/mainboard/google/gale/verstage.c
+++ b/src/mainboard/google/gale/verstage.c
@@ -24,7 +24,7 @@
static void ipq_setup_tpm(void)
{
- if (IS_ENABLED(CONFIG_I2C_TPM)) {
+ if (CONFIG(I2C_TPM)) {
gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,
GPIO_PULL_UP, GPIO_6MA, 1);
gpio_set(TPM_RESET_GPIO, 0);
diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c
index 476bcf7..8b04a65 100644
--- a/src/mainboard/google/glados/mainboard.c
+++ b/src/mainboard/google/glados/mainboard.c
@@ -73,17 +73,17 @@
printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
/* 4 Channel DMIC array. */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH))
+ if (CONFIG(NHLT_DMIC_4CH))
if (nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
/* ADI Smart Amps for left and right. */
- if (IS_ENABLED(CONFIG_NHLT_SSM4567) && adi_codec_enable())
+ if (CONFIG(NHLT_SSM4567) && adi_codec_enable())
if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
printk(BIOS_ERR, "Couldn't add ssm4567.\n");
/* MAXIM Smart Amps for left and right. */
- if (IS_ENABLED(CONFIG_NHLT_MAX98357) && max_codec_enable()) {
+ if (CONFIG(NHLT_MAX98357) && max_codec_enable()) {
if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
printk(BIOS_ERR, "Couldn't add max98357.\n");
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c
index 5eeb583..81f0866 100644
--- a/src/mainboard/google/glados/romstage.c
+++ b/src/mainboard/google/glados/romstage.c
@@ -71,6 +71,6 @@
sizeof(params->pei_data->RcompTarget));
memory_params->MemorySpdDataLen = SPD_LEN;
memory_params->DqPinsInterleaved = FALSE;
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CAROLINE))
+ if (CONFIG(BOARD_GOOGLE_CAROLINE))
memory_params->DdrFreqLimit = 1600;
}
diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c
index 5296b0f..a4a1cca 100644
--- a/src/mainboard/google/glados/smihandler.c
+++ b/src/mainboard/google/glados/smihandler.c
@@ -60,7 +60,7 @@
void mainboard_smi_sleep(u8 slp_typ)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
@@ -69,7 +69,7 @@
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h
index 41157f0..e9545de 100644
--- a/src/mainboard/google/gru/board.h
+++ b/src/mainboard/google/gru/board.h
@@ -24,7 +24,7 @@
#define GPIO_RESET GPIO(0, B, 3)
#define GPIO_SDMMC_PWR GPIO(4, D, 5)
-#if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)
+#if CONFIG(GRU_BASEBOARD_SCARLET)
#define GPIO_BL_EN GPIO(4, C, 5)
#define GPIO_BACKLIGHT GPIO(4, C, 6)
#define GPIO_EC_IN_RW GPIO(0, A, 1)
@@ -50,7 +50,7 @@
#define GPIO_WP GPIO(1, C, 2)
#endif
-#if IS_ENABLED(CONFIG_GRU_HAS_WLAN_RESET)
+#if CONFIG(GRU_HAS_WLAN_RESET)
#define GPIO_WLAN_RST_L GPIO(1, B, 3)
#else
#define GPIO_WLAN_RST_L dead_code_t(gpio_t, "no WLAN reset on this board in FW")
diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c
index 5b2985a..4630a91 100644
--- a/src/mainboard/google/gru/boardid.c
+++ b/src/mainboard/google/gru/boardid.c
@@ -22,7 +22,7 @@
static const int id_readings[] = {
/* ID : Volts : ADC value : Bucket */
/* == ===== ========= ========== */
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)
+#if CONFIG(BOARD_GOOGLE_KEVIN)
/* 0 : 0.109V: 62 : 0 - 91 */ 91,
#else
/* 0 : 0.074V: 42 : 0 - 81 */ 81,
@@ -80,7 +80,7 @@
uint32_t sku_id(void)
{
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (!CONFIG(GRU_BASEBOARD_SCARLET))
return UNDEFINED_STRAPPING_ID;
static uint32_t sku_id = UNDEFINED_STRAPPING_ID;
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 9a716ae..7c18e12 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -35,7 +35,7 @@
so that we know we can use our GPIOs reliably in following code. */
write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1 | 1 << 0));
/* On Scarlet-based boards, the 4C/4D domain is 1.8V (on others 3.0V) */
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 3));
/* Reconfigure GPIO1 from dynamic voltage selection through GPIO0_B1 to
@@ -46,10 +46,10 @@
/* Enable rails powering GPIO blocks, among other things. */
gpio_output(GPIO_P30V_EN, 1);
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (!CONFIG(GRU_BASEBOARD_SCARLET))
gpio_output(GPIO_P15V_EN, 1); /* Scarlet: EC-controlled */
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL)) {
_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
"CONSOLE_SERIAL_UART should be UART2");
@@ -89,10 +89,10 @@
static void configure_tpm(void)
{
- if (IS_ENABLED(CONFIG_GRU_HAS_TPM2)) {
+ if (CONFIG(GRU_HAS_TPM2)) {
rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) {
+ if (CONFIG(GRU_BASEBOARD_SCARLET)) {
gpio_input(GPIO(2, B, 1)); /* SPI2_MISO no-pull */
gpio_input(GPIO(2, B, 2)); /* SPI2_MOSI no-pull */
gpio_input(GPIO(2, B, 3)); /* SPI2_CLK no-pull */
diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c
index 7fb47d0..a856e45 100644
--- a/src/mainboard/google/gru/chromeos.c
+++ b/src/mainboard/google/gru/chromeos.c
@@ -21,7 +21,7 @@
#include "board.h"
-static const uint32_t wp_polarity = IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET) ?
+static const uint32_t wp_polarity = CONFIG(GRU_BASEBOARD_SCARLET) ?
ACTIVE_LOW : ACTIVE_HIGH;
int get_write_protect_state(void)
@@ -36,14 +36,14 @@
{GPIO_WP.raw, wp_polarity, gpio_get(GPIO_WP),
"write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
-#if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)
+#if CONFIG(GRU_BASEBOARD_SCARLET)
{GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"},
#endif
{GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"},
{GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"},
{GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
{GPIO_SPK_PA_EN.raw, ACTIVE_HIGH, -1, "speaker enable"},
-#if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
+#if CONFIG(GRU_HAS_TPM2)
{GPIO_TPM_IRQ.raw, ACTIVE_HIGH, -1, "TPM interrupt"},
#endif
};
@@ -53,7 +53,7 @@
void setup_chromeos_gpios(void)
{
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
gpio_input(GPIO_WP);
else
gpio_input_pullup(GPIO_WP);
@@ -61,7 +61,7 @@
gpio_input_pullup(GPIO_EC_IRQ);
}
-#if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
+#if CONFIG(GRU_HAS_TPM2)
int tis_plat_irq_status(void)
{
return gpio_irq_status(GPIO_TPM_IRQ);
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index d4fa7fc..19f4ecc 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -97,7 +97,7 @@
* 1.5V and 1.8V are EC-controlled on Scarlet derivatives,
* so we skip them.
*/
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) {
+ if (!CONFIG(GRU_BASEBOARD_SCARLET)) {
static struct bl31_gpio_param param_p15_en = {
.h = { .type = PARAM_SUSPEND_GPIO },
.gpio = { .polarity = BL31_GPIO_LEVEL_LOW },
@@ -164,7 +164,7 @@
gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */
/* set SDMMC_DET_L pin */
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
/*
* do not have external pull up, so need to
* set this pin internal pull up
@@ -178,7 +178,7 @@
* In Scarlet derivatives, this GPIO set to high will get 3v,
* With other board variants setting this GPIO low results in 3V.
*/
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
gpio_output(GPIO(2, D, 4), 1);
else
gpio_output(GPIO(2, D, 4), 0);
@@ -226,7 +226,7 @@
write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0_SD0);
write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK);
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (!CONFIG(GRU_BASEBOARD_SCARLET))
gpio_output(GPIO_P18V_AUDIO_PWREN, 1);
gpio_output(GPIO_SPK_PA_EN, 0);
@@ -239,7 +239,7 @@
* Rainier is Scarlet-derived, but uses EDP so use board-specific
* config rather than baseboard.
*/
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) {
+ if (CONFIG(BOARD_GOOGLE_SCARLET)) {
gpio_output(GPIO(4, D, 1), 0); /* DISPLAY_RST_L */
gpio_output(GPIO(4, D, 3), 1); /* PPVARP_LCD */
mdelay(10);
@@ -342,9 +342,9 @@
if (display_init_required())
configure_display();
setup_usb(0);
- if (IS_ENABLED(CONFIG_GRU_HAS_WLAN_RESET))
+ if (CONFIG(GRU_HAS_WLAN_RESET))
assert_wifi_reset();
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) {
+ if (!CONFIG(GRU_BASEBOARD_SCARLET)) {
configure_touchpad(); /* Scarlet: works differently */
setup_usb(1); /* Scarlet: only one USB port */
}
@@ -370,10 +370,10 @@
gpio_output(GPIO_BL_EN, 1); /* BL_EN */
/* Configure as output GPIO, to be toggled by payload. */
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
gpio_output(GPIO_BACKLIGHT, 0);
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
+ if (CONFIG(BOARD_GOOGLE_GRU))
prepare_backlight_i2c();
}
diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c
index 0da6539..6c64990 100644
--- a/src/mainboard/google/gru/pwm_regulator.c
+++ b/src/mainboard/google/gru/pwm_regulator.c
@@ -58,12 +58,12 @@
int pwm_enum_to_pwm_number[] = {
[PWM_REGULATOR_GPU] = 0,
[PWM_REGULATOR_LIT] = 2,
-#if IS_ENABLED(CONFIG_GRU_HAS_CENTERLOG_PWM)
+#if CONFIG(GRU_HAS_CENTERLOG_PWM)
[PWM_REGULATOR_CENTERLOG] = 3,
#else
[PWM_REGULATOR_CENTERLOG] = -1,
#endif
-#if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)
+#if CONFIG(GRU_BASEBOARD_SCARLET)
[PWM_REGULATOR_BIG] = 3,
#else
[PWM_REGULATOR_BIG] = 1,
@@ -78,14 +78,14 @@
voltage_min = pwm_design_voltage[pwm][0];
voltage_max = pwm_design_voltage[pwm][1];
- if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) ||
- (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) {
+ if ((CONFIG(BOARD_GOOGLE_KEVIN) && board_id() < 6) ||
+ (CONFIG(BOARD_GOOGLE_GRU) && board_id() < 2)) {
voltage_min = PWM_DESIGN_VOLTAGE_MIN_OUTDATED;
voltage_max = PWM_DESIGN_VOLTAGE_MAX_OUTDATED;
- } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6) {
+ } else if (CONFIG(BOARD_GOOGLE_KEVIN) && board_id() >= 6) {
voltage_min = kevin6_pwm_design_voltage[pwm][0];
voltage_max = kevin6_pwm_design_voltage[pwm][1];
- } else if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) {
+ } else if (CONFIG(GRU_BASEBOARD_SCARLET)) {
voltage_min = scarlet_pwm_design_voltage[pwm][0];
voltage_max = scarlet_pwm_design_voltage[pwm][1];
}
diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c
index 0b944fe..57c7165 100644
--- a/src/mainboard/google/gru/romstage.c
+++ b/src/mainboard/google/gru/romstage.c
@@ -35,9 +35,9 @@
* Kevin's logic rail has some ripple, so up the voltage a bit. Newer
* boards use a fixed 900mV regulator for centerlogic.
*/
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
+ if (CONFIG(BOARD_GOOGLE_KEVIN))
pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 925);
- else if (IS_ENABLED(CONFIG_GRU_HAS_CENTERLOG_PWM))
+ else if (CONFIG(GRU_HAS_CENTERLOG_PWM))
pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 900);
/* Allow time for the regulators to settle */
diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c
index e67f0ec..5e9e15f 100644
--- a/src/mainboard/google/gru/sdram_configs.c
+++ b/src/mainboard/google/gru/sdram_configs.c
@@ -51,7 +51,7 @@
static enum dram_speeds get_sdram_target_mhz(void)
{
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_BOB) && board_id() < 4)
+ if (CONFIG(BOARD_GOOGLE_BOB) && board_id() < 4)
return dram_800MHz;
return dram_928MHz;
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index e6321ba..243c627 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -43,7 +43,7 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c
index 9735ca0..8a8b223 100644
--- a/src/mainboard/google/jecht/lan.c
+++ b/src/mainboard/google/jecht/lan.c
@@ -115,7 +115,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c
index d7faafb..9c3878f3 100644
--- a/src/mainboard/google/jecht/led.c
+++ b/src/mainboard/google/jecht/led.c
@@ -21,7 +21,7 @@
{
int polarity;
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) {
+ if (CONFIG(BOARD_GOOGLE_TIDUS)) {
polarity = state == LED_OFF ? 0x00 : 0x01;
} else {
polarity = state == LED_BLINK ? 0x01 : 0x00;
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
index ef807fc..3705feb 100644
--- a/src/mainboard/google/jecht/romstage.c
+++ b/src/mainboard/google/jecht/romstage.c
@@ -47,7 +47,7 @@
/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);
- if (IS_ENABLED(CONFIG_CHROMEOS))
+ if (CONFIG(CHROMEOS))
init_bootmode_straps();
}
diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c
index 8a9e2a6..9475361 100644
--- a/src/mainboard/google/jecht/smihandler.c
+++ b/src/mainboard/google/jecht/smihandler.c
@@ -59,7 +59,7 @@
set_power_led(LED_BLINK);
/* Enable DCP mode */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) {
+ if (CONFIG(BOARD_GOOGLE_TIDUS)) {
set_gpio(GPIO_USB_CTL_1, 0);
}
break;
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 5c480bf..886e14f 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -58,7 +58,7 @@
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA))
+ if (CONFIG(BOARD_GOOGLE_LIARA))
PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
else
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 8531fc0..038cfe2 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -34,7 +34,7 @@
void bootblock_mainboard_init(void)
{
- if (IS_ENABLED(CONFIG_EM100)) {
+ if (CONFIG(EM100)) {
/*
* We should be able to rely on defaults, but it seems safer
* to explicitly set up these registers.
diff --git a/src/mainboard/google/kahlee/smihandler.c b/src/mainboard/google/kahlee/smihandler.c
index 83757a8..6e823bf 100644
--- a/src/mainboard/google/kahlee/smihandler.c
+++ b/src/mainboard/google/kahlee/smihandler.c
@@ -24,21 +24,21 @@
void mainboard_smi_gpi(u32 gpi_sts)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
if (gpi_sts & (1 << EC_SMI_GPI))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(u8 slp_typ)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
index 518d457..996e610 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
@@ -82,7 +82,7 @@
static char oem_bin_data[11];
static const char *manuf;
- if (!IS_ENABLED(CONFIG_USE_OEM_BIN))
+ if (!CONFIG(USE_OEM_BIN))
return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER;
if (manuf)
diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c
index b1d6736..ff910fe 100644
--- a/src/mainboard/google/kukui/boardid.c
+++ b/src/mainboard/google/kukui/boardid.c
@@ -69,7 +69,7 @@
static uint32_t cached_sku_id = BOARD_ID_INIT;
/* On Flapjack, getting the SKU via CBI. */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_FLAPJACK)) {
+ if (CONFIG(BOARD_GOOGLE_FLAPJACK)) {
if (cached_sku_id == BOARD_ID_INIT &&
google_chromeec_cbi_get_sku_id(&cached_sku_id))
cached_sku_id = FLAPJACK_UNDEF_SKU_ID;
@@ -77,7 +77,7 @@
}
/* Quirk for KUKUI: All P1/SKU0 had incorrectly set SKU=1. */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KUKUI)) {
+ if (CONFIG(BOARD_GOOGLE_KUKUI)) {
if (cached_sku_id == BOARD_ID_INIT && board_id() == 1) {
cached_sku_id = 0;
return cached_sku_id;
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 7d0e9c2..81ae9c5 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -24,7 +24,7 @@
void platform_romstage_main(void)
{
/* This will be done in verstage if CONFIG_VBOOT is enabled. */
- if (!IS_ENABLED(CONFIG_VBOOT))
+ if (!CONFIG(VBOOT))
mainboard_early_init();
mt6358_init();
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
index f6f36117..0ff4364 100644
--- a/src/mainboard/google/link/acpi_tables.c
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -45,7 +45,7 @@
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index 6c896fc..04b03ba 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -20,7 +20,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <arch/acpi.h>
@@ -50,7 +50,7 @@
*/
}
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
static int int15_handler(void)
{
int res = 0;
@@ -202,7 +202,7 @@
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = link_onboard_smbios_data;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c
index f2b5500..96ae1cc 100644
--- a/src/mainboard/google/link/mainboard_smi.c
+++ b/src/mainboard/google/link/mainboard_smi.c
@@ -32,7 +32,7 @@
{
u8 cmd = google_chromeec_get_event();
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 098ebaf..5cc7f6e 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -81,7 +81,7 @@
cbmem_initialize_empty();
/* This was already called from verstage in vboot context. */
- if (!IS_ENABLED(CONFIG_VBOOT))
+ if (!CONFIG(VBOOT))
early_mainboard_init();
run_ramstage();
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 098ebaf..5cc7f6e 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -81,7 +81,7 @@
cbmem_initialize_empty();
/* This was already called from verstage in vboot context. */
- if (!IS_ENABLED(CONFIG_VBOOT))
+ if (!CONFIG(VBOOT))
early_mainboard_init();
run_ramstage();
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index 35b58d8..7a1b5fa 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -50,7 +50,7 @@
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
-#if !IS_ENABLED(CONFIG_VBOOT)
+#if !CONFIG(VBOOT)
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
@@ -85,7 +85,7 @@
cbmem_initialize_empty();
/* This was already called from verstage in vboot context. */
- if (!IS_ENABLED(CONFIG_VBOOT))
+ if (!CONFIG(VBOOT))
early_mainboard_init();
run_ramstage();
@@ -94,7 +94,7 @@
/* Stub to force arm_init_caches to the top, before any stack/memory accesses */
void main(void)
{
-#if !IS_ENABLED(CONFIG_VBOOT)
+#if !CONFIG(VBOOT)
asm volatile ("bl arm_init_caches"
::: "r0","r1","r2","r3","r4","r5","ip");
#endif
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 3c705e8..4df7eeb 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -87,7 +87,7 @@
/* Init i2c bus 2 Timing register for TPM */
mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
- if (IS_ENABLED(CONFIG_OAK_HAS_TPM2))
+ if (CONFIG(OAK_HAS_TPM2))
gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h
index 6662671..84d9419 100644
--- a/src/mainboard/google/oak/gpio.h
+++ b/src/mainboard/google/oak/gpio.h
@@ -17,7 +17,7 @@
#define __MAINBOARD_GOOGLE_OAK_GPIO_H__
#include <soc/gpio.h>
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)
+#if CONFIG(BOARD_GOOGLE_ROWAN)
#define LID GPIO(KPROW1)
#define RAM_ID_1 GPIO(DSI_TE)
#define RAM_ID_2 GPIO(RDP1_A)
diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c
index 7ffa746..21525fa 100644
--- a/src/mainboard/google/oak/mainboard.c
+++ b/src/mainboard/google/oak/mainboard.c
@@ -127,7 +127,7 @@
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 3) {
/* Type C port 0 Over current alert pin */
gpio_input_pullup(GPIO(MSDC3_DSL));
- if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) {
+ if (!CONFIG(BOARD_GOOGLE_ROWAN)) {
/* Enable USB3 type A port 0 5V load switch */
gpio_output(GPIO(CM2MCLK), 1);
/* USB3 Type A port 0 power over current alert pin */
@@ -150,7 +150,7 @@
static void configure_usb_hub(void)
{
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN))
+ if (CONFIG(BOARD_GOOGLE_ROWAN))
return;
/* set usb hub reset pin (low active) to high */
@@ -278,7 +278,7 @@
u32 mipi_dsi_flags;
bool dual_dsi_mode;
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) {
+ if (CONFIG(BOARD_GOOGLE_ROWAN)) {
edid = rowan_boe_edid;
dual_dsi_mode = true;
mipi_dsi_flags = MIPI_DSI_MODE_VIDEO |
@@ -327,7 +327,7 @@
if (display_init_required()) {
mtcmos_display_power_on();
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) {
+ if (CONFIG(BOARD_GOOGLE_ROWAN)) {
configure_backlight_rowan();
configure_display_rowan();
} else {
diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c
index 43349a0..c5bd996 100644
--- a/src/mainboard/google/octopus/romstage.c
+++ b/src/mainboard/google/octopus/romstage.c
@@ -37,12 +37,12 @@
char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
const char *part_num = NULL;
- if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI)) {
+ if (!CONFIG(DRAM_PART_NUM_IN_CBI)) {
save_dimm_info_by_sku_config();
return;
}
- if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) {
+ if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) {
/* Fall back on part numbers encoded in lp4cfg array. */
if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) {
save_dimm_info_by_sku_config();
diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c
index 0ff376f..aec2ba2 100644
--- a/src/mainboard/google/octopus/variants/baseboard/memory.c
+++ b/src/mainboard/google/octopus/variants/baseboard/memory.c
@@ -205,10 +205,10 @@
const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
{
- if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI))
+ if (!CONFIG(DRAM_PART_NUM_IN_CBI))
return &non_cbi_lp4cfg;
- if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) {
+ if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) {
/* Fall back non cbi memory config. */
if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN)
return &non_cbi_lp4cfg;
diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c
index b73bbc9..914f71c 100644
--- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c
+++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c
@@ -32,13 +32,13 @@
* Headset codec is bi-directional but uses the same configuration
* settings for render and capture endpoints.
*/
- if (IS_ENABLED(CONFIG_NHLT_DA7219)) {
+ if (CONFIG(NHLT_DA7219)) {
/* Dialog for Headset codec */
if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2))
printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
}
- if (IS_ENABLED(CONFIG_NHLT_RT5682)) {
+ if (CONFIG(NHLT_RT5682)) {
/* Realtek for Headset codec */
if (!nhlt_soc_add_rt5682(nhlt, AUDIO_LINK_SSP2))
printk(BIOS_ERR, "Added ALC5682 codec.\n");
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
index 61dcde1..7d196e9 100644
--- a/src/mainboard/google/parrot/acpi_tables.c
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -47,7 +47,7 @@
gnvs->s5u1 = 0;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = parrot_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c
index e49dfce..5883cdc 100644
--- a/src/mainboard/google/parrot/smihandler.c
+++ b/src/mainboard/google/parrot/smihandler.c
@@ -29,7 +29,7 @@
static u8 mainboard_smi_ec(void)
{
u8 src;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
static int battery_critical_logged;
#endif
@@ -39,7 +39,7 @@
switch (src) {
case EC_BATTERY_CRITICAL:
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
if (!battery_critical_logged)
elog_add_event_byte(ELOG_TYPE_EC_EVENT,
EC_EVENT_BATTERY_CRITICAL);
@@ -49,7 +49,7 @@
case EC_LID_CLOSE:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
#endif
/* Go to S5 */
@@ -70,7 +70,7 @@
else if (gpi_sts & (1 << EC_LID_GPI)) {
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
#endif
/* Go to S5 */
diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl
index 0001867..34862df 100644
--- a/src/mainboard/google/poppy/dsdt.asl
+++ b/src/mainboard/google/poppy/dsdt.asl
@@ -46,7 +46,7 @@
}
}
-#if IS_ENABLED(CONFIG_VARIANT_HAS_CAMERA_ACPI)
+#if CONFIG(VARIANT_HAS_CAMERA_ACPI)
/* Camera */
#include <variant/acpi/camera.asl>
#endif
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index 6802de9..59eeefb 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -20,7 +20,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <arch/acpi.h>
@@ -37,7 +37,7 @@
{
}
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
static int int15_handler(void)
{
int res = 1;
@@ -126,7 +126,7 @@
static void mainboard_init(struct device *dev)
{
mainboard_ec_init();
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) || IS_ENABLED(CONFIG_BOARD_GOOGLE_SUMO)
+#if CONFIG(BOARD_GOOGLE_NINJA) || CONFIG(BOARD_GOOGLE_SUMO)
lan_init();
#endif
}
@@ -166,7 +166,7 @@
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
index 113e7ce..94f7b2b 100644
--- a/src/mainboard/google/rambi/mainboard_smi.c
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -34,7 +34,7 @@
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c
index 87df672..93ecc3a 100644
--- a/src/mainboard/google/rambi/variants/ninja/lan.c
+++ b/src/mainboard/google/rambi/variants/ninja/lan.c
@@ -114,7 +114,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c
index 5dae431..9a3c130 100644
--- a/src/mainboard/google/rambi/variants/sumo/lan.c
+++ b/src/mainboard/google/rambi/variants/sumo/lan.c
@@ -114,7 +114,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index 6bc5190..1743860 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -38,14 +38,14 @@
pads = variant_sleep_gpio_table(slp_typ, &num);
gpio_configure_pads(pads, num);
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c
index 8e42b93..f2ef80f 100644
--- a/src/mainboard/google/reef/variants/baseboard/nhlt.c
+++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c
@@ -23,15 +23,15 @@
void __weak variant_nhlt_init(struct nhlt *nhlt)
{
/* 1-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
+ if (CONFIG(NHLT_DMIC_1CH_16B) &&
(!nhlt_soc_add_dmic_array(nhlt, 1)))
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
/* 2-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
+ if (CONFIG(NHLT_DMIC_2CH_16B) &&
(!nhlt_soc_add_dmic_array(nhlt, 2)))
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
/* 4-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
+ if (CONFIG(NHLT_DMIC_4CH_16B) &&
(!nhlt_soc_add_dmic_array(nhlt, 4)))
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
/* Dialog for Headset codec.
diff --git a/src/mainboard/google/reef/variants/snappy/mainboard.c b/src/mainboard/google/reef/variants/snappy/mainboard.c
index 73de67e..950a029 100644
--- a/src/mainboard/google/reef/variants/snappy/mainboard.c
+++ b/src/mainboard/google/reef/variants/snappy/mainboard.c
@@ -56,7 +56,7 @@
board_sku_num = sku_strapping_value();
- if (!IS_ENABLED(CONFIG_CHROMEOS))
+ if (!CONFIG(CHROMEOS))
return board_sku_num;
if (!vpd_gets(vpd_skuid, vpd_buffer, ARRAY_SIZE(vpd_buffer), VPD_ANY))
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index 642e240..e5b0cca 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -42,7 +42,7 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* VPD support */
@@ -57,7 +57,7 @@
/* Low power idle table */
#include <soc/intel/cannonlake/acpi/lpit.asl>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_WILCO)
+#if CONFIG(EC_GOOGLE_WILCO)
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
diff --git a/src/mainboard/google/sarien/variants/sarien/ramstage.c b/src/mainboard/google/sarien/variants/sarien/ramstage.c
index ab79678..d20260c 100644
--- a/src/mainboard/google/sarien/variants/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/variants/sarien/ramstage.c
@@ -43,7 +43,7 @@
struct drivers_i2c_hid_config *info;
/* Look for VPD key that indicates which touchscreen is present */
- if (IS_ENABLED(CONFIG_VPD) &&
+ if (CONFIG(VPD) &&
!vpd_gets(TOUCHSCREEN_VPD_KEY, touchscreen_hid,
ARRAY_SIZE(touchscreen_hid), VPD_ANY))
printk(BIOS_INFO, "%s: VPD key '%s' not found, default to %s\n",
diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c
index 0ffd054..c748fb4 100644
--- a/src/mainboard/google/slippy/acpi_tables.c
+++ b/src/mainboard/google/slippy/acpi_tables.c
@@ -52,7 +52,7 @@
gnvs->tpmp = 1;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c
index bab764a..81a772c 100644
--- a/src/mainboard/google/slippy/smihandler.c
+++ b/src/mainboard/google/slippy/smihandler.c
@@ -41,7 +41,7 @@
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c
index 162456e..37d49bd 100644
--- a/src/mainboard/google/smaug/mainboard.c
+++ b/src/mainboard/google/smaug/mainboard.c
@@ -217,7 +217,7 @@
void lb_board(struct lb_header *header)
{
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
lb_table_add_serialno_from_vpd(header);
#endif
soc_add_mtc(header);
diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c
index b5dbbea..fdff5ab 100644
--- a/src/mainboard/google/storm/mainboard.c
+++ b/src/mainboard/google/storm/mainboard.c
@@ -31,7 +31,7 @@
static void setup_usb(void)
{
-#if !IS_ENABLED(CONFIG_BOARD_VARIANT_AP148)
+#if !CONFIG(BOARD_VARIANT_AP148)
gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO,
GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE);
gpio_set(USB_ENABLE_GPIO, 1);
@@ -90,7 +90,7 @@
/* Functionally a 0-cost no-op if NAND is not present */
board_nand_init();
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Copy WIFI calibration data into CBMEM. */
cbmem_add_vpd_calibration_data();
#endif
@@ -124,7 +124,7 @@
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = REGION_SIZE(dma_coherent);
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
#endif
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index 9fbdcfc..0830456 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -49,7 +49,7 @@
gnvs->s5u1 = 0;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = get_recovery_mode_switch() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c
index 6c89508..a54b80b 100644
--- a/src/mainboard/google/stout/ec.c
+++ b/src/mainboard/google/stout/ec.c
@@ -75,7 +75,7 @@
if (ec_reg & 0x8) {
printk(BIOS_ERR, " EC Fan Error\n");
critical_shutdown = 1;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_FAN_ERROR);
#endif
}
@@ -85,7 +85,7 @@
if (ec_reg & 0x80) {
printk(BIOS_ERR, " EC Thermal Device Error\n");
critical_shutdown = 1;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_THERMAL);
#endif
}
@@ -97,14 +97,14 @@
if ((ec_reg & 0xCF) == 0xC0) {
printk(BIOS_ERR, " EC Critical Battery Error\n");
critical_shutdown = 1;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL);
#endif
}
if ((ec_reg & 0x8F) == 0x8F) {
printk(BIOS_ERR, " EC Read Battery Error\n");
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY);
#endif
}
diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c
index 11584116..3eaad34 100644
--- a/src/mainboard/google/urara/mainboard.c
+++ b/src/mainboard/google/urara/mainboard.c
@@ -22,7 +22,7 @@
static void mainboard_init(struct device *dev)
{
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Copy WIFI calibration data into CBMEM. */
cbmem_add_vpd_calibration_data();
#endif
@@ -48,7 +48,7 @@
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = REGION_SIZE(dma_coherent);
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
#endif
diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c
index 604b399..c9c68cc 100644
--- a/src/mainboard/google/veyron/boardid.c
+++ b/src/mainboard/google/veyron/boardid.c
@@ -38,7 +38,7 @@
gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
- if (IS_ENABLED(CONFIG_VEYRON_FORCE_BINARY_RAM_CODE))
+ if (CONFIG(VEYRON_FORCE_BINARY_RAM_CODE))
code = gpio_base2_value(pins, ARRAY_SIZE(pins));
else
code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c
index 4c2f143..86834bf 100644
--- a/src/mainboard/google/veyron/bootblock.c
+++ b/src/mainboard/google/veyron/bootblock.c
@@ -31,7 +31,7 @@
void bootblock_mainboard_early_init()
{
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c
index d9a07e7..18047f2 100644
--- a/src/mainboard/google/veyron_mickey/bootblock.c
+++ b/src/mainboard/google/veyron_mickey/bootblock.c
@@ -31,7 +31,7 @@
void bootblock_mainboard_early_init()
{
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index 909a8ef..73f57d1 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -31,7 +31,7 @@
void bootblock_mainboard_early_init()
{
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
diff --git a/src/mainboard/hp/abm/OemCustomize.c b/src/mainboard/hp/abm/OemCustomize.c
index f3c5515..424b68a 100644
--- a/src/mainboard/hp/abm/OemCustomize.c
+++ b/src/mainboard/hp/abm/OemCustomize.c
@@ -96,7 +96,7 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
index a1b5a09..2d6499f 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
+++ b/src/mainboard/hp/compaq_8200_elite_sff/mainboard.c
@@ -19,7 +19,7 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <smbios.h>
-#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
+#if CONFIG(GENERATE_SMBIOS_TABLES)
static int mainboard_smbios_data(struct device *dev, int *handle,
unsigned long *current)
{
@@ -45,7 +45,7 @@
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
+#if CONFIG(GENERATE_SMBIOS_TABLES)
dev->ops->get_smbios_data = mainboard_smbios_data;
#endif
}
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
index 6ea302d..4b64068 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
+++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
@@ -69,7 +69,7 @@
void mainboard_config_superio(void)
{
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+ if (CONFIG(CONSOLE_SERIAL))
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index f6c72da..f204632 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -30,7 +30,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 7eaff57..66c480e 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -149,7 +149,7 @@
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -157,7 +157,7 @@
wait_all_other_cores_started(bsp_apicid);
#endif
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
index 9c6c9b6..2b1ac04 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
@@ -102,7 +102,7 @@
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
@@ -170,7 +170,7 @@
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{
- FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
}
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
index 11d6c6a..43786af 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/OemCustomize.c
@@ -167,7 +167,7 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 7ab5eb1..c6d62ed 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -168,7 +168,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
-#if IS_ENABLED(CONFIG_GFXUMA)
+#if CONFIG(GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
index 942941d..30c1026 100644
--- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
+++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
@@ -38,7 +38,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 734679d..ea67b62 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -131,7 +131,7 @@
*/
wait_all_core0_started();
- #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+ #if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -145,7 +145,7 @@
rs780_early_setup();
sb7xx_51xx_early_setup();
- #if IS_ENABLED(CONFIG_SET_FIDVID)
+ #if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c
index 631adea..f013f69 100644
--- a/src/mainboard/intel/apollolake_rvp/romstage.c
+++ b/src/mainboard/intel/apollolake_rvp/romstage.c
@@ -122,7 +122,7 @@
mupd->FspmConfig.LowMemoryMaxValue = 0;
mupd->FspmConfig.HighMemoryMaxValue = 0;
- if (IS_ENABLED(CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1))
+ if (CONFIG(BOARD_INTEL_APOLLOLAKE_RVP1))
rvp1_fill_memory_params(mupd);
else
rvp2_fill_memory_params(mupd);
diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c
index c5293dc..af2101f 100644
--- a/src/mainboard/intel/baskingridge/acpi_tables.c
+++ b/src/mainboard/intel/baskingridge/acpi_tables.c
@@ -71,7 +71,7 @@
gnvs->tpmp = 1;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Emerald Lake has no EC (?) */
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif
diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c
index 9424855..3280878 100644
--- a/src/mainboard/intel/bayleybay_fsp/mainboard.c
+++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c
@@ -19,7 +19,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <arch/interrupt.h>
diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c
index c34d82f..0b8c16b 100644
--- a/src/mainboard/intel/bayleybay_fsp/romstage.c
+++ b/src/mainboard/intel/bayleybay_fsp/romstage.c
@@ -163,7 +163,7 @@
UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig;
/* Disable 2nd DIMM on Bakersport*/
-#if IS_ENABLED(CONFIG_BOARD_INTEL_BAKERSPORT_FSP)
+#if CONFIG(BOARD_INTEL_BAKERSPORT_FSP)
UpdData->PcdMrcInitSPDAddr2 = 0x00; /* cannot use SPD_ADDR_DISABLED at this point */
#endif
}
diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c
index 946a453..88cfb1d 100644
--- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c
+++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c
@@ -19,7 +19,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <arch/interrupt.h>
diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
index 88b69da..c719d23 100644
--- a/src/mainboard/intel/cannonlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -39,7 +39,7 @@
}
}
- #if IS_ENABLED(CONFIG_CHROMEOS)
+ #if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
index 390929e..5ceff51 100644
--- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
+++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
@@ -44,7 +44,7 @@
const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
+ if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU))
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
else
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
@@ -57,7 +57,7 @@
const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
+ if (CONFIG(BOARD_INTEL_CANNONLAKE_RVPU))
memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u));
else
memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y));
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
index a1354da..2455422 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
@@ -163,7 +163,7 @@
/* D23 : SPP_MCLK */
PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* E0 : SATAXPCIE_0_SATAGP_0 */
-#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)
+#if CONFIG(BOARD_INTEL_CANNONLAKE_RVPY)
PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),
#endif
/* E1 : SATAXPCIE_1_SATAGP_1 */
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
index f3be0e8..343b721 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/nhlt.c
@@ -21,19 +21,19 @@
void __weak variant_nhlt_init(struct nhlt *nhlt)
{
/* 1-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
+ if (CONFIG(NHLT_DMIC_1CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 1))
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
/* 2-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
+ if (CONFIG(NHLT_DMIC_2CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 2))
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
/* 4-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
+ if (CONFIG(NHLT_DMIC_4CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT))
+ if (CONFIG(INCLUDE_SND_MAX98357_DA7219_NHLT))
{
/* Dialog for Headset codec.
* Headset codec is bi-directional but uses the same configuration
@@ -47,7 +47,7 @@
printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
}
- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) &&
+ if (CONFIG(INCLUDE_SND_MAX98373_NHLT) &&
!nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1))
printk(BIOS_ERR, "Added Maxim_98373 codec.\n");
}
diff --git a/src/mainboard/intel/coffeelake_rvp/dsdt.asl b/src/mainboard/intel/coffeelake_rvp/dsdt.asl
index 2ccf3b7..70d0bd6 100644
--- a/src/mainboard/intel/coffeelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/coffeelake_rvp/dsdt.asl
@@ -39,7 +39,7 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
index fc35050..b0091bd 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
@@ -17,7 +17,7 @@
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
-#if !IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H)
+#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)
static const struct pad_config gpio_table[] = {
/* GPPC */
/* A0 : RCINB_TIME_SYNC_1 */
@@ -264,7 +264,7 @@
/* H21 : GPPC_H_21 */
/* H22 : GPPC_H_22 */
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
-#if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP)
+#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP)
PAD_CFG_GPO(GPP_H22, 1, PLTRST),
#else
PAD_CFG_GPI(GPP_H22, NONE, DEEP),
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
index 161cc5f..34b161f 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/nhlt.c
@@ -21,19 +21,19 @@
void __weak variant_nhlt_init(struct nhlt *nhlt)
{
/* 1-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
+ if (CONFIG(NHLT_DMIC_1CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 1))
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
/* 2-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
+ if (CONFIG(NHLT_DMIC_2CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 2))
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
/* 4-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
+ if (CONFIG(NHLT_DMIC_4CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)) {
+ if (CONFIG(INCLUDE_SND_MAX98357_DA7219_NHLT)) {
/* Dialog for Headset codec.
* Headset codec is bi-directional but uses the same
* configuration settings for render and capture endpoints.
@@ -46,7 +46,7 @@
printk(BIOS_ERR, "Added Maxim_98357 codec.\n");
}
- if (IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT) &&
+ if (CONFIG(INCLUDE_SND_MAX98373_NHLT) &&
!nhlt_soc_add_max98373(nhlt, AUDIO_LINK_SSP1))
printk(BIOS_ERR, "Added Maxim_98373 codec.\n");
}
diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl
index 8adc853..20c71a3 100644
--- a/src/mainboard/intel/dcp847ske/acpi/superio.asl
+++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl
@@ -19,7 +19,7 @@
#define SUPERIO_DEV SIO0
#define SUPERIO_PNP_BASE 0x4e
-#if !IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS)
+#if !CONFIG(DISABLE_UART_ON_TESTPADS)
#define NCT6776_SHOW_SP1 1
#endif
#define NCT6776_SHOW_HWM 1
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index 1a46f8b..5100735 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -27,7 +27,7 @@
#include "superio.h"
#include "thermal.h"
-#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS)
+#if CONFIG(DISABLE_UART_ON_TESTPADS)
#define DEBUG_UART_EN 0
#else
#define DEBUG_UART_EN COMA_LPC_EN
@@ -46,7 +46,7 @@
/* Disable devices */
RCBA32(FD) |= PCH_DISABLE_P2P | PCH_DISABLE_XHCI;
-#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if CONFIG(USE_NATIVE_RAMINIT)
/* Enable Gigabit Ethernet */
if (RCBA32(BUC) & PCH_DISABLE_GBE) {
RCBA32(BUC) &= ~PCH_DISABLE_GBE;
@@ -125,7 +125,7 @@
SUPERIO_INITVAL(0x1a, 0x02),
SUPERIO_INITVAL(0x1b, 0x6a),
SUPERIO_INITVAL(0x27, 0x80),
-#if IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS)
+#if CONFIG(DISABLE_UART_ON_TESTPADS)
SUPERIO_INITVAL(0x2a, 0x80),
#else
SUPERIO_INITVAL(0x2a, 0x00),
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index ad31bba..24ec912 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -18,13 +18,13 @@
#include <stdint.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
-#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if CONFIG(USE_NATIVE_RAMINIT)
#include <northbridge/intel/sandybridge/raminit_native.h>
#else
#include <northbridge/intel/sandybridge/raminit.h>
#endif
-#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if !CONFIG(USE_NATIVE_RAMINIT)
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
struct pei_data pei_data_template = {
diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c
index 1791ee3..1fd7fce 100644
--- a/src/mainboard/intel/galileo/gpio.c
+++ b/src/mainboard/intel/galileo/gpio.c
@@ -25,15 +25,15 @@
const struct reg_script *script;
/* Initialize the GPIO controllers */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
script = gen2_gpio_init;
else
script = gen1_gpio_init;
reg_script_run(script);
/* Initialize the RXD and TXD paths for UART0 */
- if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) {
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(ENABLE_BUILTIN_HSUART0)) {
+ if (CONFIG(GALILEO_GEN2))
script = gen2_hsuart0;
else
script = (reg_legacy_gpio_read(
@@ -51,7 +51,7 @@
printk(BIOS_INFO, "Galileo I2C chip initialization\n");
/* Determine the correct script for the board */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
script = gen2_i2c_init;
else
/* Determine which I2C address is in use */
@@ -69,7 +69,7 @@
uint32_t value;
/* Determine the correct PCIe reset pin */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
pin_number = GEN2_PCI_RESET_RESUMEWELL_GPIO;
else
pin_number = GEN1_PCI_RESET_RESUMEWELL_GPIO;
diff --git a/src/mainboard/intel/galileo/mainboard.c b/src/mainboard/intel/galileo/mainboard.c
index 2a8ade7..0237916 100644
--- a/src/mainboard/intel/galileo/mainboard.c
+++ b/src/mainboard/intel/galileo/mainboard.c
@@ -18,7 +18,7 @@
/* Set the board version */
const char *smbios_mainboard_version(void)
{
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
return "Gen 2";
return "1.0";
}
diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c
index a5b74a0..b78ed1b 100644
--- a/src/mainboard/intel/galileo/vboot.c
+++ b/src/mainboard/intel/galileo/vboot.c
@@ -60,7 +60,7 @@
*/
/* Determine the correct script for the board */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
script = gen2_i2c_init;
else
/* Determine which I2C address is in use */
@@ -86,7 +86,7 @@
*/
/* Determine the correct script for the board */
- if (IS_ENABLED(CONFIG_GALILEO_GEN2))
+ if (CONFIG(GALILEO_GEN2))
script = gen2_tpm_reset;
else
/* Determine which I2C address is in use */
diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c
index 9c5aa6d..0676eac 100644
--- a/src/mainboard/intel/glkrvp/boardid.c
+++ b/src/mainboard/intel/glkrvp/boardid.c
@@ -27,7 +27,7 @@
{
MAYBE_STATIC int id = -1;
if (id < 0) {
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
id = variant_board_id();
else {
if (send_ec_command(EC_FAB_ID_CMD) == 0)
diff --git a/src/mainboard/intel/glkrvp/ec.c b/src/mainboard/intel/glkrvp/ec.c
index 0138a9c..44b7824 100644
--- a/src/mainboard/intel/glkrvp/ec.c
+++ b/src/mainboard/intel/glkrvp/ec.c
@@ -54,7 +54,7 @@
void mainboard_ec_init(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
if (ENV_RAMSTAGE)
ramstage_ec_init();
else if (ENV_BOOTBLOCK)
@@ -69,7 +69,7 @@
| LPC_IOE_LGE_200);
}
- if (IS_ENABLED(CONFIG_GLK_INTEL_EC)) {
+ if (CONFIG(GLK_INTEL_EC)) {
printk(BIOS_ERR, "S3 Hack Enable ACPI mode: outb(0xaa,0x66)\n");
outb(0xaa, 0x66);
printk(BIOS_INFO, "Hack to turn on the CPU fan\n");
diff --git a/src/mainboard/intel/glkrvp/romstage.c b/src/mainboard/intel/glkrvp/romstage.c
index 8e13590..7811d06 100644
--- a/src/mainboard/intel/glkrvp/romstage.c
+++ b/src/mainboard/intel/glkrvp/romstage.c
@@ -211,7 +211,7 @@
{
uint8_t boardid;
- if (IS_ENABLED(CONFIG_IS_GLK_RVP_1))
+ if (CONFIG(IS_GLK_RVP_1))
boardid = BOARD_ID_GLK_RVP1_DDR4;
else
boardid = BOARD_ID_GLK_RVP2_LP4;
diff --git a/src/mainboard/intel/glkrvp/smihandler.c b/src/mainboard/intel/glkrvp/smihandler.c
index f6d98e5..9af8993 100644
--- a/src/mainboard/intel/glkrvp/smihandler.c
+++ b/src/mainboard/intel/glkrvp/smihandler.c
@@ -25,7 +25,7 @@
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
if (gpi_status_get(sts, EC_SMI_GPI))
chromeec_smi_process_events();
}
@@ -38,14 +38,14 @@
pads = variant_sleep_gpio_table(&num);
gpio_configure_pads(pads, num);
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
@@ -53,6 +53,6 @@
void mainboard_smi_espi_handler(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_process_events();
}
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
index 8df1dc4..69a0a91 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/boardid.c
@@ -21,7 +21,7 @@
{
MAYBE_STATIC uint32_t id = BOARD_ID_INIT;
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
if (id == BOARD_ID_INIT) {
if (google_chromeec_get_board_version(&id))
id = BOARD_ID_UNKNOWN;
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
index 03f2147..3cbb4bc 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
@@ -91,7 +91,7 @@
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD),/*LPSS_UART2_RXD*/
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD),/*LPSS_UART2_TXD*/
PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxDRxE, DISPUPD),/*RF_KILL_WWAN */
-#if IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)
+#if CONFIG(TPM_ON_FAST_SPI)
PAD_CFG_GPI_INT(GPIO_67, UP_20K, DEEP, LEVEL),/*SPI TPM Interrupt */
#endif
PAD_CFG_NF(GPIO_68, UP_20K, DEEP, NF1),/*PMC_SPI_FS0*/
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
index dc23abd..170e87c 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h
@@ -22,7 +22,7 @@
* GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0
* which is North community
*/
-#if IS_ENABLED(CONFIG_SOC_ESPI)
+#if CONFIG(SOC_ESPI)
#define EC_SCI_GPI GPE0A_ESPI_SCI_STS
#else
#define EC_SCI_GPI GPE0_DW1_05
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
index 5433bd5..c35a292 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/nhlt.c
@@ -21,15 +21,15 @@
void __weak variant_nhlt_init(struct nhlt *nhlt)
{
/* 1-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
+ if (CONFIG(NHLT_DMIC_1CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 1))
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
/* 2-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
+ if (CONFIG(NHLT_DMIC_2CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 2))
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
/* 4-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
+ if (CONFIG(NHLT_DMIC_4CH_16B) &&
!nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c
index e3a0a01..44fdc4f 100644
--- a/src/mainboard/intel/harcuvar/romstage.c
+++ b/src/mainboard/intel/harcuvar/romstage.c
@@ -22,7 +22,7 @@
#include <fsp/soc_binding.h>
#include <string.h>
-#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
+#if CONFIG(ENABLE_FSP_MEMORY_DOWN)
/*
* Define platform specific Memory Down Configure structure.
@@ -118,7 +118,7 @@
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
-#if IS_ENABLED(CONFIG_ENABLE_FSP_MEMORY_DOWN)
+#if CONFIG(ENABLE_FSP_MEMORY_DOWN)
uint8_t *spd_data_ptr = NULL;
/* Get SPD data pointer */
diff --git a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
index 49ae2e6..ef2e164 100644
--- a/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
+++ b/src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
@@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
Scope (\_SB)
{
Device (PWRB)
diff --git a/src/mainboard/intel/icelake_rvp/board_id.c b/src/mainboard/intel/icelake_rvp/board_id.c
index 6ac312a..b56f047 100644
--- a/src/mainboard/intel/icelake_rvp/board_id.c
+++ b/src/mainboard/intel/icelake_rvp/board_id.c
@@ -34,7 +34,7 @@
MAYBE_STATIC int id = -1;
if (id < 0) {
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
id = get_board_id_via_ext_ec();
else{
uint8_t buffer[2];
diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl
index 53feeb9..ad469fa 100644
--- a/src/mainboard/intel/icelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/icelake_rvp/dsdt.asl
@@ -43,12 +43,12 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl
index a9a61dd..efed4de 100644
--- a/src/mainboard/intel/kblrvp/acpi/ec.asl
+++ b/src/mainboard/intel/kblrvp/acpi/ec.asl
@@ -22,7 +22,7 @@
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Enable LID switch and provide wake pin for EC */
#define EC_ENABLE_LID_SWITCH
diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
index 544d695..531cd21 100644
--- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl
+++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
Scope (\_SB)
{
Device (PWRB)
diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c
index d48c9c2..101b04b 100644
--- a/src/mainboard/intel/kblrvp/chromeos.c
+++ b/src/mainboard/intel/kblrvp/chromeos.c
@@ -43,7 +43,7 @@
int get_lid_switch(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
/* Read lid switch state from the EC. */
return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
@@ -53,7 +53,7 @@
int get_recovery_mode_switch(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) {
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
/* Check for dedicated recovery switch first. */
if (google_chromeec_get_switches() &
EC_SWITCH_DEDICATED_RECOVERY)
@@ -70,7 +70,7 @@
int clear_recovery_mode_switch(void)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
/* Clear keyboard recovery event. */
return google_chromeec_clear_events_b(
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl
index ddb69da..8a16551 100644
--- a/src/mainboard/intel/kblrvp/dsdt.asl
+++ b/src/mainboard/intel/kblrvp/dsdt.asl
@@ -51,7 +51,7 @@
#include "acpi/ipu_mainboard.asl"
#include "acpi/mipi_camera.asl"
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/intel/kblrvp/hda_verb.c b/src/mainboard/intel/kblrvp/hda_verb.c
index bbe0af0..fdd196d 100644
--- a/src/mainboard/intel/kblrvp/hda_verb.c
+++ b/src/mainboard/intel/kblrvp/hda_verb.c
@@ -14,6 +14,6 @@
* GNU General Public License for more details.
*/
-#if !IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)
+#if !CONFIG(BOARD_INTEL_KBLRVP8)
#include "variant/hda_verb.h"
#endif
diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c
index 38279c3..604c069 100644
--- a/src/mainboard/intel/kblrvp/mainboard.c
+++ b/src/mainboard/intel/kblrvp/mainboard.c
@@ -27,7 +27,7 @@
static void mainboard_init(struct device *dev)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
mainboard_ec_init();
}
diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index 0b52f37..ad55c26 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -32,7 +32,7 @@
static void ioexpander_init(void *unused)
{
- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP11))
+ if (CONFIG(BOARD_INTEL_KBLRVP11))
return;
printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n");
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c
index 8e5ffcf..c96f791 100644
--- a/src/mainboard/intel/kblrvp/romstage.c
+++ b/src/mainboard/intel/kblrvp/romstage.c
@@ -42,7 +42,7 @@
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) {
+ if (CONFIG(BOARD_INTEL_KBLRVP3)) {
struct region_device spd_rdev;
mem_cfg->DqPinsInterleaved = 0;
diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c
index bb09d78..ba8458b 100644
--- a/src/mainboard/intel/kblrvp/smihandler.c
+++ b/src/mainboard/intel/kblrvp/smihandler.c
@@ -47,25 +47,25 @@
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
{
- if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8))
+ if (CONFIG(BOARD_INTEL_KBLRVP8))
return;
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
if (gpi_status_get(sts, EC_SMI_GPI))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(u8 slp_typ)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c
index 64cc34b..df02601 100644
--- a/src/mainboard/intel/kunimitsu/smihandler.c
+++ b/src/mainboard/intel/kunimitsu/smihandler.c
@@ -54,14 +54,14 @@
void mainboard_smi_sleep(u8 slp_typ)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c
index efd20a5..9ff0639 100644
--- a/src/mainboard/intel/strago/ec.c
+++ b/src/mainboard/intel/strago/ec.c
@@ -33,7 +33,7 @@
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
post_code(0xf1);
diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c
index 6cd01e2..052e830 100644
--- a/src/mainboard/intel/strago/smihandler.c
+++ b/src/mainboard/intel/strago/smihandler.c
@@ -54,14 +54,14 @@
return 1;
}
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
@@ -88,7 +88,7 @@
*/
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
@@ -102,7 +102,7 @@
/* Disable USB charging if required */
switch (slp_typ) {
case ACPI_S3:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -117,7 +117,7 @@
enable_gpe(WAKE_GPIO_EN);
break;
case ACPI_S5:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -131,7 +131,7 @@
break;
}
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
@@ -150,7 +150,7 @@
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
@@ -159,7 +159,7 @@
#endif
break;
case APM_CNT_ACPI_DISABLE:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c
index ade9c79..cbf436b 100644
--- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c
+++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c
@@ -37,7 +37,7 @@
pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
/* I/O APICs: APIC ID Version State Address */
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 588203c..e8126d591 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -136,7 +136,7 @@
*/
wait_all_core0_started();
- #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+ #if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -150,7 +150,7 @@
rs780_early_setup();
sb7xx_51xx_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c
index c2a8721..26e02a0 100644
--- a/src/mainboard/kontron/ktqm77/mainboard.c
+++ b/src/mainboard/kontron/ktqm77/mainboard.c
@@ -21,7 +21,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
@@ -29,7 +29,7 @@
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
static int int15_handler(void)
{
int res = 0;
@@ -162,8 +162,8 @@
static void mainboard_enable(struct device *dev)
{
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) || \
- IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
+#if CONFIG(PCI_OPTION_ROM_RUN_YABEL) || \
+ CONFIG(PCI_OPTION_ROM_RUN_REALMODE)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c
index 9c6c9b6..2b1ac04 100644
--- a/src/mainboard/lenovo/g505s/BiosCallOuts.c
+++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c
@@ -102,7 +102,7 @@
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
- if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) {
+ if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
/* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
@@ -170,7 +170,7 @@
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{
- FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
}
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
diff --git a/src/mainboard/lenovo/g505s/OemCustomize.c b/src/mainboard/lenovo/g505s/OemCustomize.c
index e61dd4a..f842129 100644
--- a/src/mainboard/lenovo/g505s/OemCustomize.c
+++ b/src/mainboard/lenovo/g505s/OemCustomize.c
@@ -174,7 +174,7 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchReset->Xhci1Enable = FALSE;
}
diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c
index 3eaa8b0..c3e40ce 100644
--- a/src/mainboard/lenovo/g505s/buildOpts.c
+++ b/src/mainboard/lenovo/g505s/buildOpts.c
@@ -168,7 +168,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
-#if IS_ENABLED(CONFIG_GFXUMA)
+#if CONFIG(GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index f4830fc..03ee4db 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -43,7 +43,7 @@
pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0);
/* Enable external USB port power. */
- if (IS_ENABLED(CONFIG_USBDEBUG))
+ if (CONFIG(USBDEBUG))
ec_mm_set_bit(0x3b, 4);
}
diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c
index c502d6a..b3cac1d 100644
--- a/src/mainboard/msi/ms7721/BiosCallOuts.c
+++ b/src/mainboard/msi/ms7721/BiosCallOuts.c
@@ -65,7 +65,7 @@
void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
{
- FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+ FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
}
void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c
index 98b3478..4782e11 100644
--- a/src/mainboard/msi/ms7721/OemCustomize.c
+++ b/src/mainboard/msi/ms7721/OemCustomize.c
@@ -150,8 +150,8 @@
void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
{
FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
- FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
- FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+ FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
}
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c
index f160745..9e57e39 100644
--- a/src/mainboard/msi/ms7721/buildOpts.c
+++ b/src/mainboard/msi/ms7721/buildOpts.c
@@ -167,7 +167,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
-#if IS_ENABLED(CONFIG_GFXUMA)
+#if CONFIG(GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c
index 29880f4..0266eff 100644
--- a/src/mainboard/msi/ms7721/romstage.c
+++ b/src/mainboard/msi/ms7721/romstage.c
@@ -117,9 +117,9 @@
u8 byte;
pci_devfn_t dev;
- if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+ if (CONFIG(POST_DEVICE_PCI_PCIE))
hudson_pci_port80();
- else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+ else if (CONFIG(POST_DEVICE_LPC))
hudson_lpc_port80();
/* enable SIO LPC decode */
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
index 8c7f921..74b14b4 100644
--- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
+++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
@@ -69,7 +69,7 @@
}
/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+ if (CONFIG(LOGICAL_CPUS)) {
apicid_base = get_apicid_base(1);
printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base);
} else {
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index ab9b0a4..11015f6 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -175,7 +175,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -186,7 +186,7 @@
post_code(0x38);
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c
index f1a3a20..93c2a58 100644
--- a/src/mainboard/ocp/monolake/mainboard.c
+++ b/src/mainboard/ocp/monolake/mainboard.c
@@ -15,7 +15,7 @@
*/
#include <device/device.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
diff --git a/src/mainboard/ocp/wedge100s/mainboard.c b/src/mainboard/ocp/wedge100s/mainboard.c
index f1a3a20..93c2a58 100644
--- a/src/mainboard/ocp/wedge100s/mainboard.c
+++ b/src/mainboard/ocp/wedge100s/mainboard.c
@@ -15,7 +15,7 @@
*/
#include <device/device.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c
index b8da280..7fdc981 100644
--- a/src/mainboard/ocp/wedge100s/romstage.c
+++ b/src/mainboard/ocp/wedge100s/romstage.c
@@ -38,7 +38,7 @@
pci_write_config32(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), LPC_GEN1_DEC,
(0 << 16) | ALIGN_DOWN(SUPERIO_DEV, 4) | 1);
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+ if (CONFIG(CONSOLE_SERIAL))
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -76,7 +76,7 @@
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
UPD_DATA_REGION *fsp_upd_data = FspRtBuffer->Common.UpdDataRgnPtr;
- if (IS_ENABLED(CONFIG_FSP_USES_UPD)) {
+ if (CONFIG(FSP_USES_UPD)) {
/* The internal UART operates on 0x3f8/0x2f8.
* As it's not wired up and conflicts with SuperIO decoding
* the same range, make sure to disable it.
@@ -91,7 +91,7 @@
fsp_upd_data->SerialPortBaudRate = 0;
/* Make FSP use serial IO */
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+ if (CONFIG(CONSOLE_SERIAL))
fsp_upd_data->SerialPortType = 1;
else
fsp_upd_data->SerialPortType = 0;
diff --git a/src/mainboard/opencellular/elgon/bootblock.c b/src/mainboard/opencellular/elgon/bootblock.c
index 9dfd1b8..c7f2639 100644
--- a/src/mainboard/opencellular/elgon/bootblock.c
+++ b/src/mainboard/opencellular/elgon/bootblock.c
@@ -31,7 +31,7 @@
/* Turn off error LED */
gpio_output(ELGON_GPIO_ERROR_LED, 0);
- if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+ if (CONFIG(BOOTBLOCK_CONSOLE)) {
if (!uart_is_enabled(CONFIG_UART_FOR_CONSOLE))
uart_setup(CONFIG_UART_FOR_CONSOLE, CONFIG_TTYS0_BAUD);
}
diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c
index 8a960cf..3faa462 100644
--- a/src/mainboard/pcengines/apu2/BiosCallOuts.c
+++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c
@@ -72,7 +72,7 @@
FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
FchParams->FchReset.SataEnable = hudson_sata_enable();
FchParams->FchReset.IdeEnable = hudson_ide_enable();
- FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->FchReset.Xhci1Enable = FALSE;
} else if (StdHeader->Func == AMD_INIT_ENV) {
FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
@@ -85,13 +85,13 @@
oem_fan_control(FchParams);
/* XHCI configuration */
- FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
FchParams->Usb.Xhci1Enable = FALSE;
/* EHCI configuration */
- FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+ FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE);
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2)) {
+ if (CONFIG(BOARD_PCENGINES_APU2)) {
// Disable EHCI 0 (port 0 to 3)
FchParams->Usb.Ehci1Enable = FALSE;
} else {
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
index 16bbf8a..472b864 100644
--- a/src/mainboard/pcengines/apu2/mainboard.c
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -142,16 +142,16 @@
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO0);
if (uart)
- uart->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_UART_C);
+ uart->enabled = CONFIG(APU2_PINMUX_UART_C);
if (gpio)
- gpio->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_GPIO0);
+ gpio->enabled = CONFIG(APU2_PINMUX_GPIO0);
uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4);
gpio = dev_find_slot_pnp(SIO_PORT, NCT5104D_GPIO1);
if (uart)
- uart->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_UART_D);
+ uart->enabled = CONFIG(APU2_PINMUX_UART_D);
if (gpio)
- gpio->enabled = IS_ENABLED(CONFIG_APU2_PINMUX_GPIO1);
+ gpio->enabled = CONFIG(APU2_PINMUX_GPIO1);
}
/**********************************************
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 49281b9..c449cc1 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -79,7 +79,7 @@
/* COM2 on apu5 is reserved so only COM1 should be supported */
if ((CONFIG_UART_FOR_CONSOLE == 1) &&
- !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
+ !CONFIG(BOARD_PCENGINES_APU5))
nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
else if (CONFIG_UART_FOR_CONSOLE == 0)
nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
@@ -143,13 +143,13 @@
//
// Configure output disabled, value low, pull up/down disabled
//
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {
+ if (CONFIG(BOARD_PCENGINES_APU5)) {
configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting);
}
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) ||
- IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
- IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
+ if (CONFIG(BOARD_PCENGINES_APU2) ||
+ CONFIG(BOARD_PCENGINES_APU3) ||
+ CONFIG(BOARD_PCENGINES_APU4)) {
configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
}
@@ -161,8 +161,8 @@
// Configure output enabled, value low, pull up/down disabled
//
setting = GPIO_OUTPUT_ENABLE;
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
- IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
+ if (CONFIG(BOARD_PCENGINES_APU3) ||
+ CONFIG(BOARD_PCENGINES_APU4)) {
configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
}
@@ -175,7 +175,7 @@
//
setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE;
- if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {
+ if (CONFIG(BOARD_PCENGINES_APU5)) {
configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
}
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
index e1364b6..0c3d3dbb 100644
--- a/src/mainboard/samsung/lumpy/acpi_tables.c
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -21,7 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <ec/acpi/ec.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif
#include <southbridge/intel/bd82x6x/nvs.h>
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 1bb0b79..74d491f 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -30,7 +30,7 @@
#include <southbridge/intel/common/gpio.h>
#include <halt.h>
#include "option_table.h"
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
+#if CONFIG(DRIVERS_UART_8250IO)
#include <superio/smsc/lpc47n207/lpc47n207.h>
#endif
@@ -39,7 +39,7 @@
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
+#if CONFIG(DRIVERS_UART_8250IO)
/* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 8370cfe..9450aa1 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -30,12 +30,12 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <halt.h>
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
+#if CONFIG(DRIVERS_UART_8250IO)
#include <superio/smsc/lpc47n207/lpc47n207.h>
#endif
/* Stumpy USB Reset Disable defined in cmos.layout */
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
+#if CONFIG(USE_OPTION_TABLE)
#include "option_table.h"
#define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3)
#else
@@ -52,7 +52,7 @@
/* Set COM1/COM2 decode range */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
-#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
+#if CONFIG(DRIVERS_UART_8250IO)
/* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\
CNF2_LPC_EN | COMA_LPC_EN);
diff --git a/src/mainboard/scaleway/tagada/bootblock.c b/src/mainboard/scaleway/tagada/bootblock.c
index b926275..b03583c 100644
--- a/src/mainboard/scaleway/tagada/bootblock.c
+++ b/src/mainboard/scaleway/tagada/bootblock.c
@@ -24,6 +24,6 @@
void bootblock_mainboard_init(void)
{
- if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE))
+ if (CONFIG(BOOTBLOCK_CONSOLE))
printk(BIOS_SPEW, "Board Serial: %s.\n", bmcinfo_serial());
}
diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c
index 1f87378..2bb9852 100644
--- a/src/mainboard/siemens/mc_bdx1/mainboard.c
+++ b/src/mainboard/siemens/mc_bdx1/mainboard.c
@@ -23,7 +23,7 @@
#include <device/pci_ids.h>
#include <device/path.h>
#include <console/console.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <device/mmio.h>
diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c
index ecc2b27..169b04d 100644
--- a/src/mainboard/siemens/mc_tcu3/mainboard.c
+++ b/src/mainboard/siemens/mc_tcu3/mainboard.c
@@ -19,7 +19,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <arch/interrupt.h>
diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c
index 0611a6d..34c81a2 100644
--- a/src/mainboard/sifive/hifive-unleashed/romstage.c
+++ b/src/mainboard/sifive/hifive-unleashed/romstage.c
@@ -30,7 +30,7 @@
clock_init();
// re-initialize UART
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))
+ if (CONFIG(CONSOLE_SERIAL))
uart_init(CONFIG_UART_FOR_CONSOLE);
sdram_init();
diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
index 0a1e816..6279d9c 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
@@ -69,7 +69,7 @@
}
/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index d688cc9..1d6410d 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -169,7 +169,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -179,7 +179,7 @@
post_code(0x38);
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n",
msr.hi, msr.lo);
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
index 4f1fa47..f32312d 100644
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
@@ -86,7 +86,7 @@
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(3);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index bf3528d..76d255b 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -222,7 +222,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -232,7 +232,7 @@
post_code(0x38);
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 30241a0..c234d30 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -145,7 +145,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -159,7 +159,7 @@
sr5650_early_setup();
sb7xx_51xx_early_setup();
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index 1cefda9..f589ef6 100644
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -68,7 +68,7 @@
}
/*I/O APICs: APIC ID Version State Address*/
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+ if (CONFIG(LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 084fc48..73951d1 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -170,7 +170,7 @@
*/
wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -180,7 +180,7 @@
post_code(0x38);
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
msr = rdmsr(MSR_COFVID_STS);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c
index 4cfee2e..e7d65a0 100644
--- a/src/mainboard/via/epia-m850/mainboard.c
+++ b/src/mainboard/via/epia-m850/mainboard.c
@@ -19,7 +19,7 @@
#include <device/pci_ops.h>
#include <console/console.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <arch/interrupt.h>
#include <x86emu/x86emu.h>
@@ -96,7 +96,7 @@
{
(void)dev;
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
printk(BIOS_DEBUG, "Installing INT15 handler...\n");
mainboard_interrupt_handlers(0x15, &vx900_int15_handler);
#endif