coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl
index 204c1c4..a07ce3e 100644
--- a/src/mainboard/google/auron/acpi/mainboard.asl
+++ b/src/mainboard/google/auron/acpi/mainboard.asl
@@ -16,7 +16,7 @@
#include <variant/onboard.h>
-#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_BUDDY)
+#if !CONFIG(BOARD_GOOGLE_BUDDY)
Scope (\_SB.PCI0.RP01)
{
Device (WLAN)
diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c
index 247fc2f..790eeff 100644
--- a/src/mainboard/google/auron/smihandler.c
+++ b/src/mainboard/google/auron/smihandler.c
@@ -33,7 +33,7 @@
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
@@ -65,7 +65,7 @@
static void mainboard_disable_gpios(void)
{
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_SAMUS)
+#if CONFIG(BOARD_GOOGLE_SAMUS)
/* Put SSD in reset to prevent leak */
set_gpio(BOARD_SSD_RESET_GPIO, 0);
/* Disable LTE */
diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c
index d072fd9..5afb26c 100644
--- a/src/mainboard/google/auron/variants/buddy/variant.c
+++ b/src/mainboard/google/auron/variants/buddy/variant.c
@@ -131,7 +131,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c
index f7b51a9..4da0a2b 100644
--- a/src/mainboard/google/beltino/acpi_tables.c
+++ b/src/mainboard/google/beltino/acpi_tables.c
@@ -69,7 +69,7 @@
gnvs->tpmp = 1;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// SuperIO is always RO
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif
diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c
index 1d0bc43..7286437 100644
--- a/src/mainboard/google/beltino/lan.c
+++ b/src/mainboard/google/beltino/lan.c
@@ -115,7 +115,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
index 993c5e8..6b69277 100644
--- a/src/mainboard/google/butterfly/mainboard.c
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -188,7 +188,7 @@
struct device *ethernet_dev = NULL;
void *vpd_file;
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 9f98c8b..726e561 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -26,7 +26,7 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <halt.h>
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#endif
diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl
index dd6bb68..70ab862 100644
--- a/src/mainboard/google/cyan/acpi/dptf.asl
+++ b/src/mainboard/google/cyan/acpi/dptf.asl
@@ -21,6 +21,6 @@
#include <variant/acpi/dptf.asl>
/* Include SoC DPTF */
-#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA)
+#if !CONFIG(BOARD_GOOGLE_TERRA)
#include <acpi/dptf/dptf.asl>
#endif
diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c
index e7c91d2..0db5824 100644
--- a/src/mainboard/google/cyan/acpi_tables.c
+++ b/src/mainboard/google/cyan/acpi_tables.c
@@ -35,7 +35,7 @@
gnvs->dpte = 1;
/* Disable PMIC I2C port for ACPI for all boards except cyan */
- if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN))
+ if (!CONFIG(BOARD_GOOGLE_CYAN))
gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0;
}
diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c
index 752637c..4b148f8 100644
--- a/src/mainboard/google/cyan/chromeos.c
+++ b/src/mainboard/google/cyan/chromeos.c
@@ -54,7 +54,7 @@
* in the reading.
*/
#if ENV_ROMSTAGE
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+ if (CONFIG(BOARD_GOOGLE_CYAN)) {
write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0),
(PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT));
write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1),
@@ -65,7 +65,7 @@
#endif
/* WP is enabled when the pin is reading high. */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+ if (CONFIG(BOARD_GOOGLE_CYAN)) {
return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0))
& PAD_VAL_HIGH);
} else {
diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl
index 13b83b7..397f6d2 100644
--- a/src/mainboard/google/cyan/dsdt.asl
+++ b/src/mainboard/google/cyan/dsdt.asl
@@ -37,7 +37,7 @@
Device (PCI0)
{
#include <acpi/southcluster.asl>
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA)
+#if CONFIG(BOARD_GOOGLE_TERRA)
#include <variant/acpi/cpu.asl>
#else
#include <acpi/dptf/cpu.asl>
diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c
index efd20a5..9ff0639 100644
--- a/src/mainboard/google/cyan/ec.c
+++ b/src/mainboard/google/cyan/ec.c
@@ -33,7 +33,7 @@
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
post_code(0xf1);
diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c
index ef0f489..aa20593 100644
--- a/src/mainboard/google/cyan/romstage.c
+++ b/src/mainboard/google/cyan/romstage.c
@@ -33,7 +33,7 @@
MEMORY_INIT_UPD *memory_params)
{
/* Update SPD data */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+ if (CONFIG(BOARD_GOOGLE_CYAN)) {
memory_params->PcdMemoryTypeEnable = MEM_DDR3;
memory_params->PcdMemorySpdPtr =
(u32)params->pei_data->spd_data_ch0;
diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c
index 88400f7..852d9c9 100644
--- a/src/mainboard/google/cyan/smihandler.c
+++ b/src/mainboard/google/cyan/smihandler.c
@@ -55,14 +55,14 @@
return 1;
}
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
static uint8_t mainboard_smi_ec(void)
{
uint8_t cmd = google_chromeec_get_event();
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
@@ -89,7 +89,7 @@
*/
void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0)
@@ -106,7 +106,7 @@
/* Disable USB charging if required */
switch (slp_typ) {
case ACPI_S3:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s3u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -121,7 +121,7 @@
enable_gpe(WAKE_GPIO_EN);
break;
case ACPI_S5:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
if (smm_get_gnvs()->s5u0 == 0)
google_chromeec_set_usb_charge_mode(
0, USB_CHARGE_MODE_DISABLED);
@@ -145,7 +145,7 @@
break;
}
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
/* Disable SCI and SMI events */
google_chromeec_set_smi_mask(0);
google_chromeec_set_sci_mask(0);
@@ -165,7 +165,7 @@
{
switch (apmc) {
case APM_CNT_ACPI_ENABLE:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_smi_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
@@ -174,7 +174,7 @@
#endif
break;
case APM_CNT_ACPI_DISABLE:
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
google_chromeec_set_sci_mask(0);
/* Clear all pending events */
while (google_chromeec_get_event() != 0)
diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c
index b7b0c30..af694a4 100644
--- a/src/mainboard/google/cyan/spd/spd.c
+++ b/src/mainboard/google/cyan/spd/spd.c
@@ -81,7 +81,7 @@
spd_content = get_spd_pointer(spd_file,
spd_file_len / SPD_PAGE_LEN,
&dual_channel);
- if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) {
+ if (CONFIG(DISPLAY_SPD_DATA) && spd_content != NULL) {
printk(BIOS_DEBUG, "SPD Data:\n");
hexdump(spd_content, SPD_PAGE_LEN);
printk(BIOS_DEBUG, "\n");
@@ -137,7 +137,7 @@
}
/* Parse the SPD data to determine the DIMM information */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) {
+ if (CONFIG(BOARD_GOOGLE_CYAN)) {
dimm->ddr_type = MEMORY_TYPE_DDR3;
} else {
dimm->ddr_type = MEMORY_TYPE_LPDDR3;
diff --git a/src/mainboard/google/dragonegg/dsdt.asl b/src/mainboard/google/dragonegg/dsdt.asl
index 2e9ce63..ab0b977 100644
--- a/src/mainboard/google/dragonegg/dsdt.asl
+++ b/src/mainboard/google/dragonegg/dsdt.asl
@@ -43,7 +43,7 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
// Chrome OS specific
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c
index b4cb332..4cf2a85 100644
--- a/src/mainboard/google/foster/chromeos.c
+++ b/src/mainboard/google/foster/chromeos.c
@@ -68,7 +68,7 @@
int get_recovery_mode_switch(void)
{
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
uint64_t ec_events;
ec_events = google_chromeec_get_events_b();
diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c
index 9e1a0f3..5684f8f 100644
--- a/src/mainboard/google/gale/mainboard.c
+++ b/src/mainboard/google/gale/mainboard.c
@@ -46,7 +46,7 @@
setup_mmu(DRAM_INITIALIZED);
setup_usb();
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
/* Copy WIFI calibration data into CBMEM. */
cbmem_add_vpd_calibration_data();
}
@@ -80,7 +80,7 @@
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = REGION_SIZE(dma_coherent);
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
}
diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c
index 1a3f5a4..1edd8a7 100644
--- a/src/mainboard/google/gale/verstage.c
+++ b/src/mainboard/google/gale/verstage.c
@@ -24,7 +24,7 @@
static void ipq_setup_tpm(void)
{
- if (IS_ENABLED(CONFIG_I2C_TPM)) {
+ if (CONFIG(I2C_TPM)) {
gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO,
GPIO_PULL_UP, GPIO_6MA, 1);
gpio_set(TPM_RESET_GPIO, 0);
diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c
index 476bcf7..8b04a65 100644
--- a/src/mainboard/google/glados/mainboard.c
+++ b/src/mainboard/google/glados/mainboard.c
@@ -73,17 +73,17 @@
printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
/* 4 Channel DMIC array. */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH))
+ if (CONFIG(NHLT_DMIC_4CH))
if (nhlt_soc_add_dmic_array(nhlt, 4))
printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
/* ADI Smart Amps for left and right. */
- if (IS_ENABLED(CONFIG_NHLT_SSM4567) && adi_codec_enable())
+ if (CONFIG(NHLT_SSM4567) && adi_codec_enable())
if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
printk(BIOS_ERR, "Couldn't add ssm4567.\n");
/* MAXIM Smart Amps for left and right. */
- if (IS_ENABLED(CONFIG_NHLT_MAX98357) && max_codec_enable()) {
+ if (CONFIG(NHLT_MAX98357) && max_codec_enable()) {
if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
printk(BIOS_ERR, "Couldn't add max98357.\n");
diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c
index 5eeb583..81f0866 100644
--- a/src/mainboard/google/glados/romstage.c
+++ b/src/mainboard/google/glados/romstage.c
@@ -71,6 +71,6 @@
sizeof(params->pei_data->RcompTarget));
memory_params->MemorySpdDataLen = SPD_LEN;
memory_params->DqPinsInterleaved = FALSE;
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CAROLINE))
+ if (CONFIG(BOARD_GOOGLE_CAROLINE))
memory_params->DdrFreqLimit = 1600;
}
diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c
index 5296b0f..a4a1cca 100644
--- a/src/mainboard/google/glados/smihandler.c
+++ b/src/mainboard/google/glados/smihandler.c
@@ -60,7 +60,7 @@
void mainboard_smi_sleep(u8 slp_typ)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
@@ -69,7 +69,7 @@
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h
index 41157f0..e9545de 100644
--- a/src/mainboard/google/gru/board.h
+++ b/src/mainboard/google/gru/board.h
@@ -24,7 +24,7 @@
#define GPIO_RESET GPIO(0, B, 3)
#define GPIO_SDMMC_PWR GPIO(4, D, 5)
-#if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)
+#if CONFIG(GRU_BASEBOARD_SCARLET)
#define GPIO_BL_EN GPIO(4, C, 5)
#define GPIO_BACKLIGHT GPIO(4, C, 6)
#define GPIO_EC_IN_RW GPIO(0, A, 1)
@@ -50,7 +50,7 @@
#define GPIO_WP GPIO(1, C, 2)
#endif
-#if IS_ENABLED(CONFIG_GRU_HAS_WLAN_RESET)
+#if CONFIG(GRU_HAS_WLAN_RESET)
#define GPIO_WLAN_RST_L GPIO(1, B, 3)
#else
#define GPIO_WLAN_RST_L dead_code_t(gpio_t, "no WLAN reset on this board in FW")
diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c
index 5b2985a..4630a91 100644
--- a/src/mainboard/google/gru/boardid.c
+++ b/src/mainboard/google/gru/boardid.c
@@ -22,7 +22,7 @@
static const int id_readings[] = {
/* ID : Volts : ADC value : Bucket */
/* == ===== ========= ========== */
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)
+#if CONFIG(BOARD_GOOGLE_KEVIN)
/* 0 : 0.109V: 62 : 0 - 91 */ 91,
#else
/* 0 : 0.074V: 42 : 0 - 81 */ 81,
@@ -80,7 +80,7 @@
uint32_t sku_id(void)
{
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (!CONFIG(GRU_BASEBOARD_SCARLET))
return UNDEFINED_STRAPPING_ID;
static uint32_t sku_id = UNDEFINED_STRAPPING_ID;
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 9a716ae..7c18e12 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -35,7 +35,7 @@
so that we know we can use our GPIOs reliably in following code. */
write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1 | 1 << 0));
/* On Scarlet-based boards, the 4C/4D domain is 1.8V (on others 3.0V) */
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 3));
/* Reconfigure GPIO1 from dynamic voltage selection through GPIO0_B1 to
@@ -46,10 +46,10 @@
/* Enable rails powering GPIO blocks, among other things. */
gpio_output(GPIO_P30V_EN, 1);
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (!CONFIG(GRU_BASEBOARD_SCARLET))
gpio_output(GPIO_P15V_EN, 1); /* Scarlet: EC-controlled */
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL)) {
_Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE,
"CONSOLE_SERIAL_UART should be UART2");
@@ -89,10 +89,10 @@
static void configure_tpm(void)
{
- if (IS_ENABLED(CONFIG_GRU_HAS_TPM2)) {
+ if (CONFIG(GRU_HAS_TPM2)) {
rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) {
+ if (CONFIG(GRU_BASEBOARD_SCARLET)) {
gpio_input(GPIO(2, B, 1)); /* SPI2_MISO no-pull */
gpio_input(GPIO(2, B, 2)); /* SPI2_MOSI no-pull */
gpio_input(GPIO(2, B, 3)); /* SPI2_CLK no-pull */
diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c
index 7fb47d0..a856e45 100644
--- a/src/mainboard/google/gru/chromeos.c
+++ b/src/mainboard/google/gru/chromeos.c
@@ -21,7 +21,7 @@
#include "board.h"
-static const uint32_t wp_polarity = IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET) ?
+static const uint32_t wp_polarity = CONFIG(GRU_BASEBOARD_SCARLET) ?
ACTIVE_LOW : ACTIVE_HIGH;
int get_write_protect_state(void)
@@ -36,14 +36,14 @@
{GPIO_WP.raw, wp_polarity, gpio_get(GPIO_WP),
"write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
-#if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)
+#if CONFIG(GRU_BASEBOARD_SCARLET)
{GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"},
#endif
{GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"},
{GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"},
{GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
{GPIO_SPK_PA_EN.raw, ACTIVE_HIGH, -1, "speaker enable"},
-#if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
+#if CONFIG(GRU_HAS_TPM2)
{GPIO_TPM_IRQ.raw, ACTIVE_HIGH, -1, "TPM interrupt"},
#endif
};
@@ -53,7 +53,7 @@
void setup_chromeos_gpios(void)
{
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
gpio_input(GPIO_WP);
else
gpio_input_pullup(GPIO_WP);
@@ -61,7 +61,7 @@
gpio_input_pullup(GPIO_EC_IRQ);
}
-#if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
+#if CONFIG(GRU_HAS_TPM2)
int tis_plat_irq_status(void)
{
return gpio_irq_status(GPIO_TPM_IRQ);
diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c
index d4fa7fc..19f4ecc 100644
--- a/src/mainboard/google/gru/mainboard.c
+++ b/src/mainboard/google/gru/mainboard.c
@@ -97,7 +97,7 @@
* 1.5V and 1.8V are EC-controlled on Scarlet derivatives,
* so we skip them.
*/
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) {
+ if (!CONFIG(GRU_BASEBOARD_SCARLET)) {
static struct bl31_gpio_param param_p15_en = {
.h = { .type = PARAM_SUSPEND_GPIO },
.gpio = { .polarity = BL31_GPIO_LEVEL_LOW },
@@ -164,7 +164,7 @@
gpio_output(GPIO(2, A, 2), 1); /* SDMMC_SDIO_PWR_EN */
/* set SDMMC_DET_L pin */
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
/*
* do not have external pull up, so need to
* set this pin internal pull up
@@ -178,7 +178,7 @@
* In Scarlet derivatives, this GPIO set to high will get 3v,
* With other board variants setting this GPIO low results in 3V.
*/
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
gpio_output(GPIO(2, D, 4), 1);
else
gpio_output(GPIO(2, D, 4), 0);
@@ -226,7 +226,7 @@
write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0_SD0);
write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK);
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (!CONFIG(GRU_BASEBOARD_SCARLET))
gpio_output(GPIO_P18V_AUDIO_PWREN, 1);
gpio_output(GPIO_SPK_PA_EN, 0);
@@ -239,7 +239,7 @@
* Rainier is Scarlet-derived, but uses EDP so use board-specific
* config rather than baseboard.
*/
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) {
+ if (CONFIG(BOARD_GOOGLE_SCARLET)) {
gpio_output(GPIO(4, D, 1), 0); /* DISPLAY_RST_L */
gpio_output(GPIO(4, D, 3), 1); /* PPVARP_LCD */
mdelay(10);
@@ -342,9 +342,9 @@
if (display_init_required())
configure_display();
setup_usb(0);
- if (IS_ENABLED(CONFIG_GRU_HAS_WLAN_RESET))
+ if (CONFIG(GRU_HAS_WLAN_RESET))
assert_wifi_reset();
- if (!IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) {
+ if (!CONFIG(GRU_BASEBOARD_SCARLET)) {
configure_touchpad(); /* Scarlet: works differently */
setup_usb(1); /* Scarlet: only one USB port */
}
@@ -370,10 +370,10 @@
gpio_output(GPIO_BL_EN, 1); /* BL_EN */
/* Configure as output GPIO, to be toggled by payload. */
- if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET))
+ if (CONFIG(GRU_BASEBOARD_SCARLET))
gpio_output(GPIO_BACKLIGHT, 0);
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU))
+ if (CONFIG(BOARD_GOOGLE_GRU))
prepare_backlight_i2c();
}
diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c
index 0da6539..6c64990 100644
--- a/src/mainboard/google/gru/pwm_regulator.c
+++ b/src/mainboard/google/gru/pwm_regulator.c
@@ -58,12 +58,12 @@
int pwm_enum_to_pwm_number[] = {
[PWM_REGULATOR_GPU] = 0,
[PWM_REGULATOR_LIT] = 2,
-#if IS_ENABLED(CONFIG_GRU_HAS_CENTERLOG_PWM)
+#if CONFIG(GRU_HAS_CENTERLOG_PWM)
[PWM_REGULATOR_CENTERLOG] = 3,
#else
[PWM_REGULATOR_CENTERLOG] = -1,
#endif
-#if IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)
+#if CONFIG(GRU_BASEBOARD_SCARLET)
[PWM_REGULATOR_BIG] = 3,
#else
[PWM_REGULATOR_BIG] = 1,
@@ -78,14 +78,14 @@
voltage_min = pwm_design_voltage[pwm][0];
voltage_max = pwm_design_voltage[pwm][1];
- if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) ||
- (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU) && board_id() < 2)) {
+ if ((CONFIG(BOARD_GOOGLE_KEVIN) && board_id() < 6) ||
+ (CONFIG(BOARD_GOOGLE_GRU) && board_id() < 2)) {
voltage_min = PWM_DESIGN_VOLTAGE_MIN_OUTDATED;
voltage_max = PWM_DESIGN_VOLTAGE_MAX_OUTDATED;
- } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6) {
+ } else if (CONFIG(BOARD_GOOGLE_KEVIN) && board_id() >= 6) {
voltage_min = kevin6_pwm_design_voltage[pwm][0];
voltage_max = kevin6_pwm_design_voltage[pwm][1];
- } else if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) {
+ } else if (CONFIG(GRU_BASEBOARD_SCARLET)) {
voltage_min = scarlet_pwm_design_voltage[pwm][0];
voltage_max = scarlet_pwm_design_voltage[pwm][1];
}
diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c
index 0b944fe..57c7165 100644
--- a/src/mainboard/google/gru/romstage.c
+++ b/src/mainboard/google/gru/romstage.c
@@ -35,9 +35,9 @@
* Kevin's logic rail has some ripple, so up the voltage a bit. Newer
* boards use a fixed 900mV regulator for centerlogic.
*/
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN))
+ if (CONFIG(BOARD_GOOGLE_KEVIN))
pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 925);
- else if (IS_ENABLED(CONFIG_GRU_HAS_CENTERLOG_PWM))
+ else if (CONFIG(GRU_HAS_CENTERLOG_PWM))
pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 900);
/* Allow time for the regulators to settle */
diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c
index e67f0ec..5e9e15f 100644
--- a/src/mainboard/google/gru/sdram_configs.c
+++ b/src/mainboard/google/gru/sdram_configs.c
@@ -51,7 +51,7 @@
static enum dram_speeds get_sdram_target_mhz(void)
{
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_BOB) && board_id() < 4)
+ if (CONFIG(BOARD_GOOGLE_BOB) && board_id() < 4)
return dram_800MHz;
return dram_928MHz;
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index e6321ba..243c627 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -43,7 +43,7 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c
index 9735ca0..8a8b223 100644
--- a/src/mainboard/google/jecht/lan.c
+++ b/src/mainboard/google/jecht/lan.c
@@ -115,7 +115,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/jecht/led.c b/src/mainboard/google/jecht/led.c
index d7faafb..9c3878f3 100644
--- a/src/mainboard/google/jecht/led.c
+++ b/src/mainboard/google/jecht/led.c
@@ -21,7 +21,7 @@
{
int polarity;
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) {
+ if (CONFIG(BOARD_GOOGLE_TIDUS)) {
polarity = state == LED_OFF ? 0x00 : 0x01;
} else {
polarity = state == LED_BLINK ? 0x01 : 0x00;
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
index ef807fc..3705feb 100644
--- a/src/mainboard/google/jecht/romstage.c
+++ b/src/mainboard/google/jecht/romstage.c
@@ -47,7 +47,7 @@
/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);
- if (IS_ENABLED(CONFIG_CHROMEOS))
+ if (CONFIG(CHROMEOS))
init_bootmode_straps();
}
diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c
index 8a9e2a6..9475361 100644
--- a/src/mainboard/google/jecht/smihandler.c
+++ b/src/mainboard/google/jecht/smihandler.c
@@ -59,7 +59,7 @@
set_power_led(LED_BLINK);
/* Enable DCP mode */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_TIDUS)) {
+ if (CONFIG(BOARD_GOOGLE_TIDUS)) {
set_gpio(GPIO_USB_CTL_1, 0);
}
break;
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index 5c480bf..886e14f 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -58,7 +58,7 @@
void OemPostParams(AMD_POST_PARAMS *PostParams)
{
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA))
+ if (CONFIG(BOARD_GOOGLE_LIARA))
PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
else
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c
index 8531fc0..038cfe2 100644
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -34,7 +34,7 @@
void bootblock_mainboard_init(void)
{
- if (IS_ENABLED(CONFIG_EM100)) {
+ if (CONFIG(EM100)) {
/*
* We should be able to rely on defaults, but it seems safer
* to explicitly set up these registers.
diff --git a/src/mainboard/google/kahlee/smihandler.c b/src/mainboard/google/kahlee/smihandler.c
index 83757a8..6e823bf 100644
--- a/src/mainboard/google/kahlee/smihandler.c
+++ b/src/mainboard/google/kahlee/smihandler.c
@@ -24,21 +24,21 @@
void mainboard_smi_gpi(u32 gpi_sts)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
if (gpi_sts & (1 << EC_SMI_GPI))
chromeec_smi_process_events();
}
void mainboard_smi_sleep(u8 slp_typ)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
index 518d457..996e610 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
@@ -82,7 +82,7 @@
static char oem_bin_data[11];
static const char *manuf;
- if (!IS_ENABLED(CONFIG_USE_OEM_BIN))
+ if (!CONFIG(USE_OEM_BIN))
return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER;
if (manuf)
diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c
index b1d6736..ff910fe 100644
--- a/src/mainboard/google/kukui/boardid.c
+++ b/src/mainboard/google/kukui/boardid.c
@@ -69,7 +69,7 @@
static uint32_t cached_sku_id = BOARD_ID_INIT;
/* On Flapjack, getting the SKU via CBI. */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_FLAPJACK)) {
+ if (CONFIG(BOARD_GOOGLE_FLAPJACK)) {
if (cached_sku_id == BOARD_ID_INIT &&
google_chromeec_cbi_get_sku_id(&cached_sku_id))
cached_sku_id = FLAPJACK_UNDEF_SKU_ID;
@@ -77,7 +77,7 @@
}
/* Quirk for KUKUI: All P1/SKU0 had incorrectly set SKU=1. */
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KUKUI)) {
+ if (CONFIG(BOARD_GOOGLE_KUKUI)) {
if (cached_sku_id == BOARD_ID_INIT && board_id() == 1) {
cached_sku_id = 0;
return cached_sku_id;
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 7d0e9c2..81ae9c5 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -24,7 +24,7 @@
void platform_romstage_main(void)
{
/* This will be done in verstage if CONFIG_VBOOT is enabled. */
- if (!IS_ENABLED(CONFIG_VBOOT))
+ if (!CONFIG(VBOOT))
mainboard_early_init();
mt6358_init();
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
index f6f36117..0ff4364 100644
--- a/src/mainboard/google/link/acpi_tables.c
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -45,7 +45,7 @@
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
index 6c896fc..04b03ba 100644
--- a/src/mainboard/google/link/mainboard.c
+++ b/src/mainboard/google/link/mainboard.c
@@ -20,7 +20,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <arch/acpi.h>
@@ -50,7 +50,7 @@
*/
}
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
static int int15_handler(void)
{
int res = 0;
@@ -202,7 +202,7 @@
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = link_onboard_smbios_data;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c
index f2b5500..96ae1cc 100644
--- a/src/mainboard/google/link/mainboard_smi.c
+++ b/src/mainboard/google/link/mainboard_smi.c
@@ -32,7 +32,7 @@
{
u8 cmd = google_chromeec_get_event();
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 098ebaf..5cc7f6e 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -81,7 +81,7 @@
cbmem_initialize_empty();
/* This was already called from verstage in vboot context. */
- if (!IS_ENABLED(CONFIG_VBOOT))
+ if (!CONFIG(VBOOT))
early_mainboard_init();
run_ramstage();
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 098ebaf..5cc7f6e 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -81,7 +81,7 @@
cbmem_initialize_empty();
/* This was already called from verstage in vboot context. */
- if (!IS_ENABLED(CONFIG_VBOOT))
+ if (!CONFIG(VBOOT))
early_mainboard_init();
run_ramstage();
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index 35b58d8..7a1b5fa 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -50,7 +50,7 @@
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
-#if !IS_ENABLED(CONFIG_VBOOT)
+#if !CONFIG(VBOOT)
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
@@ -85,7 +85,7 @@
cbmem_initialize_empty();
/* This was already called from verstage in vboot context. */
- if (!IS_ENABLED(CONFIG_VBOOT))
+ if (!CONFIG(VBOOT))
early_mainboard_init();
run_ramstage();
@@ -94,7 +94,7 @@
/* Stub to force arm_init_caches to the top, before any stack/memory accesses */
void main(void)
{
-#if !IS_ENABLED(CONFIG_VBOOT)
+#if !CONFIG(VBOOT)
asm volatile ("bl arm_init_caches"
::: "r0","r1","r2","r3","r4","r5","ip");
#endif
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 3c705e8..4df7eeb 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -87,7 +87,7 @@
/* Init i2c bus 2 Timing register for TPM */
mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
- if (IS_ENABLED(CONFIG_OAK_HAS_TPM2))
+ if (CONFIG(OAK_HAS_TPM2))
gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
diff --git a/src/mainboard/google/oak/gpio.h b/src/mainboard/google/oak/gpio.h
index 6662671..84d9419 100644
--- a/src/mainboard/google/oak/gpio.h
+++ b/src/mainboard/google/oak/gpio.h
@@ -17,7 +17,7 @@
#define __MAINBOARD_GOOGLE_OAK_GPIO_H__
#include <soc/gpio.h>
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)
+#if CONFIG(BOARD_GOOGLE_ROWAN)
#define LID GPIO(KPROW1)
#define RAM_ID_1 GPIO(DSI_TE)
#define RAM_ID_2 GPIO(RDP1_A)
diff --git a/src/mainboard/google/oak/mainboard.c b/src/mainboard/google/oak/mainboard.c
index 7ffa746..21525fa 100644
--- a/src/mainboard/google/oak/mainboard.c
+++ b/src/mainboard/google/oak/mainboard.c
@@ -127,7 +127,7 @@
if (board_id() + CONFIG_BOARD_ID_ADJUSTMENT > 3) {
/* Type C port 0 Over current alert pin */
gpio_input_pullup(GPIO(MSDC3_DSL));
- if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) {
+ if (!CONFIG(BOARD_GOOGLE_ROWAN)) {
/* Enable USB3 type A port 0 5V load switch */
gpio_output(GPIO(CM2MCLK), 1);
/* USB3 Type A port 0 power over current alert pin */
@@ -150,7 +150,7 @@
static void configure_usb_hub(void)
{
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN))
+ if (CONFIG(BOARD_GOOGLE_ROWAN))
return;
/* set usb hub reset pin (low active) to high */
@@ -278,7 +278,7 @@
u32 mipi_dsi_flags;
bool dual_dsi_mode;
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) {
+ if (CONFIG(BOARD_GOOGLE_ROWAN)) {
edid = rowan_boe_edid;
dual_dsi_mode = true;
mipi_dsi_flags = MIPI_DSI_MODE_VIDEO |
@@ -327,7 +327,7 @@
if (display_init_required()) {
mtcmos_display_power_on();
- if (IS_ENABLED(CONFIG_BOARD_GOOGLE_ROWAN)) {
+ if (CONFIG(BOARD_GOOGLE_ROWAN)) {
configure_backlight_rowan();
configure_display_rowan();
} else {
diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c
index 43349a0..c5bd996 100644
--- a/src/mainboard/google/octopus/romstage.c
+++ b/src/mainboard/google/octopus/romstage.c
@@ -37,12 +37,12 @@
char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
const char *part_num = NULL;
- if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI)) {
+ if (!CONFIG(DRAM_PART_NUM_IN_CBI)) {
save_dimm_info_by_sku_config();
return;
}
- if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) {
+ if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) {
/* Fall back on part numbers encoded in lp4cfg array. */
if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) {
save_dimm_info_by_sku_config();
diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c
index 0ff376f..aec2ba2 100644
--- a/src/mainboard/google/octopus/variants/baseboard/memory.c
+++ b/src/mainboard/google/octopus/variants/baseboard/memory.c
@@ -205,10 +205,10 @@
const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
{
- if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI))
+ if (!CONFIG(DRAM_PART_NUM_IN_CBI))
return &non_cbi_lp4cfg;
- if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) {
+ if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) {
/* Fall back non cbi memory config. */
if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN)
return &non_cbi_lp4cfg;
diff --git a/src/mainboard/google/octopus/variants/baseboard/nhlt.c b/src/mainboard/google/octopus/variants/baseboard/nhlt.c
index b73bbc9..914f71c 100644
--- a/src/mainboard/google/octopus/variants/baseboard/nhlt.c
+++ b/src/mainboard/google/octopus/variants/baseboard/nhlt.c
@@ -32,13 +32,13 @@
* Headset codec is bi-directional but uses the same configuration
* settings for render and capture endpoints.
*/
- if (IS_ENABLED(CONFIG_NHLT_DA7219)) {
+ if (CONFIG(NHLT_DA7219)) {
/* Dialog for Headset codec */
if (!nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP2))
printk(BIOS_ERR, "Added Dialog_7219 codec.\n");
}
- if (IS_ENABLED(CONFIG_NHLT_RT5682)) {
+ if (CONFIG(NHLT_RT5682)) {
/* Realtek for Headset codec */
if (!nhlt_soc_add_rt5682(nhlt, AUDIO_LINK_SSP2))
printk(BIOS_ERR, "Added ALC5682 codec.\n");
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
index 61dcde1..7d196e9 100644
--- a/src/mainboard/google/parrot/acpi_tables.c
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -47,7 +47,7 @@
gnvs->s5u1 = 0;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = parrot_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/mainboard/google/parrot/smihandler.c b/src/mainboard/google/parrot/smihandler.c
index e49dfce..5883cdc 100644
--- a/src/mainboard/google/parrot/smihandler.c
+++ b/src/mainboard/google/parrot/smihandler.c
@@ -29,7 +29,7 @@
static u8 mainboard_smi_ec(void)
{
u8 src;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
static int battery_critical_logged;
#endif
@@ -39,7 +39,7 @@
switch (src) {
case EC_BATTERY_CRITICAL:
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
if (!battery_critical_logged)
elog_add_event_byte(ELOG_TYPE_EC_EVENT,
EC_EVENT_BATTERY_CRITICAL);
@@ -49,7 +49,7 @@
case EC_LID_CLOSE:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
#endif
/* Go to S5 */
@@ -70,7 +70,7 @@
else if (gpi_sts & (1 << EC_LID_GPI)) {
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
#endif
/* Go to S5 */
diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl
index 0001867..34862df 100644
--- a/src/mainboard/google/poppy/dsdt.asl
+++ b/src/mainboard/google/poppy/dsdt.asl
@@ -46,7 +46,7 @@
}
}
-#if IS_ENABLED(CONFIG_VARIANT_HAS_CAMERA_ACPI)
+#if CONFIG(VARIANT_HAS_CAMERA_ACPI)
/* Camera */
#include <variant/acpi/camera.asl>
#endif
diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c
index 6802de9..59eeefb 100644
--- a/src/mainboard/google/rambi/mainboard.c
+++ b/src/mainboard/google/rambi/mainboard.c
@@ -20,7 +20,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <arch/acpi.h>
@@ -37,7 +37,7 @@
{
}
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
static int int15_handler(void)
{
int res = 1;
@@ -126,7 +126,7 @@
static void mainboard_init(struct device *dev)
{
mainboard_ec_init();
-#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) || IS_ENABLED(CONFIG_BOARD_GOOGLE_SUMO)
+#if CONFIG(BOARD_GOOGLE_NINJA) || CONFIG(BOARD_GOOGLE_SUMO)
lan_init();
#endif
}
@@ -166,7 +166,7 @@
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
-#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
+#if CONFIG(VGA_ROM_RUN)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif
diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
index 113e7ce..94f7b2b 100644
--- a/src/mainboard/google/rambi/mainboard_smi.c
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -34,7 +34,7 @@
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c
index 87df672..93ecc3a 100644
--- a/src/mainboard/google/rambi/variants/ninja/lan.c
+++ b/src/mainboard/google/rambi/variants/ninja/lan.c
@@ -114,7 +114,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c
index 5dae431..9a3c130 100644
--- a/src/mainboard/google/rambi/variants/sumo/lan.c
+++ b/src/mainboard/google/rambi/variants/sumo/lan.c
@@ -114,7 +114,7 @@
u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
- if (IS_ENABLED(CONFIG_CHROMEOS)) {
+ if (CONFIG(CHROMEOS)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) {
diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index 6bc5190..1743860 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -38,14 +38,14 @@
pads = variant_sleep_gpio_table(slp_typ, &num);
gpio_configure_pads(pads, num);
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
diff --git a/src/mainboard/google/reef/variants/baseboard/nhlt.c b/src/mainboard/google/reef/variants/baseboard/nhlt.c
index 8e42b93..f2ef80f 100644
--- a/src/mainboard/google/reef/variants/baseboard/nhlt.c
+++ b/src/mainboard/google/reef/variants/baseboard/nhlt.c
@@ -23,15 +23,15 @@
void __weak variant_nhlt_init(struct nhlt *nhlt)
{
/* 1-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_1CH_16B) &&
+ if (CONFIG(NHLT_DMIC_1CH_16B) &&
(!nhlt_soc_add_dmic_array(nhlt, 1)))
printk(BIOS_ERR, "Added 1CH DMIC array.\n");
/* 2-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_2CH_16B) &&
+ if (CONFIG(NHLT_DMIC_2CH_16B) &&
(!nhlt_soc_add_dmic_array(nhlt, 2)))
printk(BIOS_ERR, "Added 2CH DMIC array.\n");
/* 4-dmic configuration */
- if (IS_ENABLED(CONFIG_NHLT_DMIC_4CH_16B) &&
+ if (CONFIG(NHLT_DMIC_4CH_16B) &&
(!nhlt_soc_add_dmic_array(nhlt, 4)))
printk(BIOS_ERR, "Added 4CH DMIC array.\n");
/* Dialog for Headset codec.
diff --git a/src/mainboard/google/reef/variants/snappy/mainboard.c b/src/mainboard/google/reef/variants/snappy/mainboard.c
index 73de67e..950a029 100644
--- a/src/mainboard/google/reef/variants/snappy/mainboard.c
+++ b/src/mainboard/google/reef/variants/snappy/mainboard.c
@@ -56,7 +56,7 @@
board_sku_num = sku_strapping_value();
- if (!IS_ENABLED(CONFIG_CHROMEOS))
+ if (!CONFIG(CHROMEOS))
return board_sku_num;
if (!vpd_gets(vpd_skuid, vpd_buffer, ARRAY_SIZE(vpd_buffer), VPD_ANY))
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index 642e240..e5b0cca 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -42,7 +42,7 @@
}
}
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* VPD support */
@@ -57,7 +57,7 @@
/* Low power idle table */
#include <soc/intel/cannonlake/acpi/lpit.asl>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_WILCO)
+#if CONFIG(EC_GOOGLE_WILCO)
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
diff --git a/src/mainboard/google/sarien/variants/sarien/ramstage.c b/src/mainboard/google/sarien/variants/sarien/ramstage.c
index ab79678..d20260c 100644
--- a/src/mainboard/google/sarien/variants/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/variants/sarien/ramstage.c
@@ -43,7 +43,7 @@
struct drivers_i2c_hid_config *info;
/* Look for VPD key that indicates which touchscreen is present */
- if (IS_ENABLED(CONFIG_VPD) &&
+ if (CONFIG(VPD) &&
!vpd_gets(TOUCHSCREEN_VPD_KEY, touchscreen_hid,
ARRAY_SIZE(touchscreen_hid), VPD_ANY))
printk(BIOS_INFO, "%s: VPD key '%s' not found, default to %s\n",
diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c
index 0ffd054..c748fb4 100644
--- a/src/mainboard/google/slippy/acpi_tables.c
+++ b/src/mainboard/google/slippy/acpi_tables.c
@@ -52,7 +52,7 @@
gnvs->tpmp = 1;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c
index bab764a..81a772c 100644
--- a/src/mainboard/google/slippy/smihandler.c
+++ b/src/mainboard/google/slippy/smihandler.c
@@ -41,7 +41,7 @@
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
diff --git a/src/mainboard/google/smaug/mainboard.c b/src/mainboard/google/smaug/mainboard.c
index 162456e..37d49bd 100644
--- a/src/mainboard/google/smaug/mainboard.c
+++ b/src/mainboard/google/smaug/mainboard.c
@@ -217,7 +217,7 @@
void lb_board(struct lb_header *header)
{
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
lb_table_add_serialno_from_vpd(header);
#endif
soc_add_mtc(header);
diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c
index b5dbbea..fdff5ab 100644
--- a/src/mainboard/google/storm/mainboard.c
+++ b/src/mainboard/google/storm/mainboard.c
@@ -31,7 +31,7 @@
static void setup_usb(void)
{
-#if !IS_ENABLED(CONFIG_BOARD_VARIANT_AP148)
+#if !CONFIG(BOARD_VARIANT_AP148)
gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO,
GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE);
gpio_set(USB_ENABLE_GPIO, 1);
@@ -90,7 +90,7 @@
/* Functionally a 0-cost no-op if NAND is not present */
board_nand_init();
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Copy WIFI calibration data into CBMEM. */
cbmem_add_vpd_calibration_data();
#endif
@@ -124,7 +124,7 @@
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = REGION_SIZE(dma_coherent);
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
#endif
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index 9fbdcfc..0830456 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -49,7 +49,7 @@
gnvs->s5u1 = 0;
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = get_recovery_mode_switch() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif
diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c
index 6c89508..a54b80b 100644
--- a/src/mainboard/google/stout/ec.c
+++ b/src/mainboard/google/stout/ec.c
@@ -75,7 +75,7 @@
if (ec_reg & 0x8) {
printk(BIOS_ERR, " EC Fan Error\n");
critical_shutdown = 1;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_FAN_ERROR);
#endif
}
@@ -85,7 +85,7 @@
if (ec_reg & 0x80) {
printk(BIOS_ERR, " EC Thermal Device Error\n");
critical_shutdown = 1;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_THERMAL);
#endif
}
@@ -97,14 +97,14 @@
if ((ec_reg & 0xCF) == 0xC0) {
printk(BIOS_ERR, " EC Critical Battery Error\n");
critical_shutdown = 1;
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL);
#endif
}
if ((ec_reg & 0x8F) == 0x8F) {
printk(BIOS_ERR, " EC Read Battery Error\n");
-#if IS_ENABLED(CONFIG_ELOG_GSMI)
+#if CONFIG(ELOG_GSMI)
elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY);
#endif
}
diff --git a/src/mainboard/google/urara/mainboard.c b/src/mainboard/google/urara/mainboard.c
index 11584116..3eaad34 100644
--- a/src/mainboard/google/urara/mainboard.c
+++ b/src/mainboard/google/urara/mainboard.c
@@ -22,7 +22,7 @@
static void mainboard_init(struct device *dev)
{
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Copy WIFI calibration data into CBMEM. */
cbmem_add_vpd_calibration_data();
#endif
@@ -48,7 +48,7 @@
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = REGION_SIZE(dma_coherent);
-#if IS_ENABLED(CONFIG_CHROMEOS)
+#if CONFIG(CHROMEOS)
/* Retrieve the switch interface MAC addresses. */
lb_table_add_macs_from_vpd(header);
#endif
diff --git a/src/mainboard/google/veyron/boardid.c b/src/mainboard/google/veyron/boardid.c
index 604b399..c9c68cc 100644
--- a/src/mainboard/google/veyron/boardid.c
+++ b/src/mainboard/google/veyron/boardid.c
@@ -38,7 +38,7 @@
gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
- if (IS_ENABLED(CONFIG_VEYRON_FORCE_BINARY_RAM_CODE))
+ if (CONFIG(VEYRON_FORCE_BINARY_RAM_CODE))
code = gpio_base2_value(pins, ARRAY_SIZE(pins));
else
code = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins));
diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c
index 4c2f143..86834bf 100644
--- a/src/mainboard/google/veyron/bootblock.c
+++ b/src/mainboard/google/veyron/bootblock.c
@@ -31,7 +31,7 @@
void bootblock_mainboard_early_init()
{
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c
index d9a07e7..18047f2 100644
--- a/src/mainboard/google/veyron_mickey/bootblock.c
+++ b/src/mainboard/google/veyron_mickey/bootblock.c
@@ -31,7 +31,7 @@
void bootblock_mainboard_early_init()
{
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index 909a8ef..73f57d1 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -31,7 +31,7 @@
void bootblock_mainboard_early_init()
{
- if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
+ if (CONFIG(CONSOLE_SERIAL)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}