coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 7788a2d..b2b915f 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -134,7 +134,7 @@
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
-#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR)
+#if CONFIG(CPU_HAS_L2_ENABLE_MSR)
/*
* Enable the L2 cache. Currently this assumes that this
* only affect socketed CPU's for which this is always valid,
@@ -152,7 +152,7 @@
invd
movl %eax, %cr0
-#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
+#if CONFIG(MICROCODE_UPDATE_PRE_RAM)
update_microcode:
/* put the return address in %esp */
movl $end_microcode_update, %esp
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 9d50582..4beac0b 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -23,7 +23,7 @@
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/* Fixed location, ASSERTED in failover.ld if it changes. */
.set ap_sipi_vector_in_rom, 0xff
#endif
@@ -318,7 +318,7 @@
invd
movl %eax, %cr0
-#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
+#if CONFIG(MICROCODE_UPDATE_PRE_RAM)
update_microcode:
/* put the return address in %esp */
movl $end_microcode_update, %esp
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 264ad4a..a7daff4 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -54,7 +54,7 @@
platform_enter_postcar();
}
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
* keeping changes in cache_as_ram.S easy to manage.
*/
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index a568ea1..a2ff65c 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -31,7 +31,7 @@
{
msr_t msr;
uint32_t feature_flag;
- int enable = IS_ENABLED(CONFIG_ENABLE_VMX);
+ int enable = CONFIG(ENABLE_VMX);
feature_flag = cpu_get_feature_flags_ecx();
/* Check that the VMX is supported before reading or writing the MSR. */
@@ -71,7 +71,7 @@
void set_feature_ctrl_lock(void)
{
msr_t msr;
- int lock = IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT);
+ int lock = CONFIG(SET_IA32_FC_LOCK_BIT);
uint32_t feature_flag = cpu_get_feature_flags_ecx();
/* Check if VMX is supported before reading or writing the MSR */
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
index 7994f0b..efa8693 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
@@ -132,7 +132,7 @@
x86_enable_cache();
/* Load microcode */
- if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+ if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
/* Clear out pending MCEs */
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index 3a306b5..722cc01 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -23,7 +23,7 @@
#include <cpu/intel/microcode/microcode.c>
#include "haswell.h"
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)
+#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/lynxpoint/pch.h>
#else
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index d5028c2..1e5f3d3 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -30,7 +30,7 @@
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#endif
#include <northbridge/intel/haswell/haswell.h>
@@ -89,7 +89,7 @@
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
@@ -131,7 +131,7 @@
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
- #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+ #if CONFIG(HAVE_ACPI_RESUME)
/* Failed S3 resume, reset to come up cleanly */
system_reset();
#endif
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index b05d3d4..f2f28f6 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -19,7 +19,7 @@
#include <smp/spinlock.h>
#include <assert.h>
-#if IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)
+#if CONFIG(PARALLEL_CPU_INIT)
#error Intel hyper-threading requires serialized CPU init
#endif
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index 48909c2..ea2d838 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -75,7 +75,7 @@
printk(BIOS_DEBUG, "SMRR status: %senabled\n",
ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
} else {
- if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT))
+ if (!CONFIG(SET_IA32_FC_LOCK_BIT))
printk(BIOS_INFO,
"Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n");
ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index ed528d1..19dbda8 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -23,7 +23,7 @@
#include <cpu/intel/microcode/microcode.c>
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)
+#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK)
#include <southbridge/intel/ibexpeak/pch.h>
#include "model_2065x.h"
#else
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 670b097..9dcbe37 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -24,8 +24,8 @@
#include <cpu/intel/microcode/microcode.c>
#include "model_206ax.h"
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) || \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
+#if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \
+ CONFIG(SOUTHBRIDGE_INTEL_C216)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/bd82x6x/pch.h>
#else
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index fc0db17..d348df6 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -24,7 +24,7 @@
/* Turn on caching if we haven't already */
x86_enable_cache();
- if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
+ if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
@@ -37,7 +37,7 @@
setup_lapic();
/* Start up my CPU siblings */
- if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+ if (!CONFIG(PARALLEL_MP))
intel_sibling_init(cpu);
};
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 4b824a5..cc2a895 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -175,7 +175,7 @@
}
/* Adjust available SMM handler memory size. */
- if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
+ if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE);
params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
}
diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
index c31f4c0..12cbfc0 100644
--- a/src/cpu/intel/turbo/turbo.c
+++ b/src/cpu/intel/turbo/turbo.c
@@ -19,7 +19,7 @@
#include <cpu/x86/msr.h>
#include <arch/cpu.h>
-#if IS_ENABLED(CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)
+#if CONFIG(CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)
static inline int get_global_turbo_state(void)
{
return TURBO_UNKNOWN;