coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index 96d6cdc..0693ded 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -34,7 +34,7 @@
msr_t msr;
int num_banks;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -65,7 +65,7 @@
/* Set the processor name string */
// init_processor_name();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index 3086f15..1516a6b 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -33,7 +33,7 @@
msr_t msr;
int num_banks;
int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
printk(BIOS_DEBUG, "Model 14 Init.\n");
@@ -83,7 +83,7 @@
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index 7528431..26b20dc 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -37,7 +37,7 @@
int num_banks;
int msrno;
unsigned int cpu_idx;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -82,7 +82,7 @@
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
@@ -102,7 +102,7 @@
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (CONFIG(HAVE_SMI_HANDLER)) {
cpu_idx = cpu_info()->index;
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
index 188f95c..e6fb0db 100644
--- a/src/cpu/amd/agesa/family16kb/model_16_init.c
+++ b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -35,7 +35,7 @@
msr_t msr;
int num_banks;
int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -80,7 +80,7 @@
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index e4c2704..f923a47 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -141,7 +141,7 @@
CAR_FAM10_errata_applied:
-#if IS_ENABLED(CONFIG_MMCONF_SUPPORT)
+#if CONFIG(MMCONF_SUPPORT)
#if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
#error "MMCONF_BASE_ADDRESS too big"
#elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
@@ -315,7 +315,7 @@
*/
.endm
-#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
+#if CONFIG(CPU_AMD_MODEL_10XXX)
#if CacheSize > 0x80000
#error Invalid CAR size, must be at most 128k (processor limit is 512k).
#endif
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index b1d0c5a..199a453 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -80,7 +80,7 @@
family = amd_fam1x_cpu_family();
-#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
+#if CONFIG(CPU_AMD_MODEL_10XXX)
if (family >= 0x6f) {
/* Family 15h or later */
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index e55ef40..18e7542 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -36,7 +36,7 @@
#error "You need to set CONFIG_RAMTOP greater than 1M"
#endif
-#if IS_ENABLED(CONFIG_DEBUG_CAR)
+#if CONFIG(DEBUG_CAR)
#define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg)
#else
#define print_car_debug(format, arg...)
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
index 428924d..db58f5d 100644
--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
+++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
@@ -95,21 +95,21 @@
static inline void print_debug_fv(const char *str, u32 val)
{
-#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
+#if CONFIG(SET_FIDVID_DEBUG)
printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif
}
static inline void print_debug_fv_8(const char *str, u8 val)
{
-#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
+#if CONFIG(SET_FIDVID_DEBUG)
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif
}
static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
{
-#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
+#if CONFIG(SET_FIDVID_DEBUG)
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif
}
@@ -505,7 +505,7 @@
}
/* TODO: look into C1E state and F3xA0[IdleExitEn]*/
- #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)
+ #if CONFIG(SVI_HIGH_FREQ)
if (cpuRev & AMD_FAM10_C3) {
dword |= SVI_HIGH_FREQ_ON;
}
@@ -585,7 +585,7 @@
if (cpuRev & AMD_DR_Bx ) {
smaf001 = 0xA6;
} else {
- #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)
+ #if CONFIG(SVI_HIGH_FREQ)
if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
smaf001 = 0xF6;
}
@@ -1036,7 +1036,7 @@
}
-#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)
+#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
struct ap_apicid_st {
u32 num;
// it could use 256 bytes for 64 node quad core system
@@ -1055,7 +1055,7 @@
int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
{
-#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)
+#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
struct ap_apicid_st ap_apicidx;
u32 i;
#endif
@@ -1070,8 +1070,8 @@
print_debug_fv("BSP fid = ", fv.common_fid);
-#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \
- !IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)
+#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \
+ !CONFIG(SET_FIDVID_CORE0_ONLY)
/* For all APs (We know the APIC ID of all APs even when the APIC ID
is lifted) remote read from AP LAPIC_MSG_REG about max fid.
Then calculate the common max fid that can be used for all
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c
index 57d4424..76bc6d9 100644
--- a/src/cpu/amd/family_10h-family_15h/init_cpus.c
+++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c
@@ -18,7 +18,7 @@
#include <device/pci_ops.h>
#include "init_cpus.h"
-#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
+#if CONFIG(HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
#include <pc80/mc146818rtc.h>
@@ -30,17 +30,17 @@
#include <southbridge/amd/common/reset.h>
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
+#if CONFIG(SOUTHBRIDGE_AMD_SB700)
#include <southbridge/amd/sb700/sb700.h>
#endif
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
+#if CONFIG(SOUTHBRIDGE_AMD_SB800)
#include <southbridge/amd/sb800/sb800.h>
#endif
#include "cpu/amd/car/disable_cache_as_ram.c"
-#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
+#if CONFIG(PCI_IO_CFG_EXT)
static void set_EnableCf8ExtCfg(void)
{
// set the NB_CFG_MSR[46]=1;
@@ -156,7 +156,7 @@
/* get_nodes define in ht_wrapper.c */
nodes = get_nodes();
- if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) ||
+ if (!CONFIG(LOGICAL_CPUS) ||
read_option(multi_core, 0) != 0) { // 0 means multi core
disable_siblings = 1;
} else {
@@ -186,8 +186,8 @@
for (j = jstart; j <= jend; j++) {
ap_apicid = get_boot_apic_id(i, j);
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
-#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
+#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
+#if !CONFIG(LIFT_BSP_APIC_ID)
if ((i != 0) || (j != 0)) /* except bsp */
#endif
ap_apicid += CONFIG_APIC_ID_OFFSET;
@@ -231,7 +231,7 @@
return result;
}
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
#endif
@@ -402,17 +402,17 @@
if (!is_fam15h())
set_apicid_cpuid_lo();
set_EnableCf8ExtCfg();
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)
+#if CONFIG(ENABLE_APIC_EXT_ID)
enable_apic_ext_id(id.nodeid);
#endif
}
enable_lapic();
-#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
+#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
u32 initial_apicid = get_initial_apicid();
-#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
+#if !CONFIG(LIFT_BSP_APIC_ID)
if (initial_apicid != 0) // other than bsp
#endif
{
@@ -424,7 +424,7 @@
lapic_write(LAPIC_ID, dword);
}
-#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
+#if CONFIG(LIFT_BSP_APIC_ID)
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif
@@ -477,8 +477,8 @@
}
}
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)
+#if CONFIG(SET_FIDVID)
+#if CONFIG(LOGICAL_CPUS) && CONFIG(SET_FIDVID_CORE0_ONLY)
// Run on all AP for proper FID/VID setup.
if (id.coreid == 0) // only need set fid for core0
#endif
@@ -501,7 +501,7 @@
if (is_fam15h()) {
/* core 1 on node 0 is special; to avoid corrupting the
* BSP do not alter MTRRs on that core */
- if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+ if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1;
else
fam15_bsp_core1_apicid = 1;
@@ -578,7 +578,7 @@
/* Enable routing table */
printk(BIOS_DEBUG, "Start node %02x", node);
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
+#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
/* For FAM10 support, we need to set Dram base/limit for the new node */
pci_write_config32(NODE_MP(node), 0x44, 0);
pci_write_config32(NODE_MP(node), 0x40, 3);
@@ -1040,7 +1040,7 @@
}
}
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
+#if CONFIG(SOUTHBRIDGE_AMD_SB700) || CONFIG(SOUTHBRIDGE_AMD_SB800)
if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
/* Set up message triggered C1E */
msr = rdmsr(MSR_INTPEND);
@@ -1060,7 +1060,7 @@
if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) {
enable_c_states = 0;
- if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
+ if (CONFIG(HAVE_ACPI_TABLES))
if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
enable_c_states = !!nvram;
@@ -1869,7 +1869,7 @@
cpuSetAMDPCI(i);
}
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
// Prep each node for FID/VID setup.
prep_fid_change();
#endif
@@ -1883,6 +1883,6 @@
#endif
}
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
# include "fidvid.c"
#endif
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index 674ba78..9819caf 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -62,7 +62,7 @@
msr_t msr;
int num_banks;
struct node_core_id id;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
uint8_t delay_start;
@@ -123,7 +123,7 @@
/* Set the processor name string */
init_processor_name();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
@@ -204,7 +204,7 @@
wrmsr(BU_CFG2_MSR, msr);
}
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (CONFIG(HAVE_SMI_HANDLER)) {
printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
/* Set SMM base address for this CPU */
diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
index 15b6550..d024069 100644
--- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
@@ -187,7 +187,7 @@
uint8_t enable_c_states;
enable_c_states = 0;
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+#if CONFIG(HAVE_ACPI_TABLES)
if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
enable_c_states = !!nvram;
#endif
diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c
index 344dc77..1433e07 100644
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c
+++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c
@@ -44,7 +44,7 @@
uint64_t get_uma_memory_size(uint64_t topmem)
{
uint64_t uma_size = 0;
- if (IS_ENABLED(CONFIG_GFXUMA)) {
+ if (CONFIG(GFXUMA)) {
/* refer to UMA Size Consideration in 780 BDG. */
if (topmem >= 0x40000000) /* 1GB and above system memory */
uma_size = 0x10000000; /* 256M recommended UMA */
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 783675d..584041e 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -200,7 +200,7 @@
}
#ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_lock(romstage_microcode_cbfs_lock());
#endif
#endif
@@ -210,7 +210,7 @@
if (!ucode) {
UCODE_DEBUG("microcode file not found. Skipping updates.\n");
#ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
@@ -220,7 +220,7 @@
amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
#ifdef __PRE_RAM__
-#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index ae2a2df..10fd9f5 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -88,7 +88,7 @@
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
- if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
+ if (CONFIG(UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c
index 5455b0c..3a641bf 100644
--- a/src/cpu/amd/pi/00630F01/model_15_init.c
+++ b/src/cpu/amd/pi/00630F01/model_15_init.c
@@ -36,7 +36,7 @@
int num_banks;
int msrno;
unsigned int cpu_idx;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -78,7 +78,7 @@
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
@@ -98,7 +98,7 @@
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (CONFIG(HAVE_SMI_HANDLER)) {
cpu_idx = cpu_info()->index;
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index e028b6f..2cbeab8 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -94,7 +94,7 @@
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
- if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
+ if (CONFIG(UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c
index d156525..65d87c2 100644
--- a/src/cpu/amd/pi/00660F01/model_15_init.c
+++ b/src/cpu/amd/pi/00660F01/model_15_init.c
@@ -51,7 +51,7 @@
msr_t msr;
int num_banks;
int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -90,7 +90,7 @@
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index 163066b..3769319 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -99,7 +99,7 @@
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
- if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
+ if (CONFIG(UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c
index 7ae89b4..5678c5f 100644
--- a/src/cpu/amd/pi/00730F01/model_16_init.c
+++ b/src/cpu/amd/pi/00730F01/model_16_init.c
@@ -34,7 +34,7 @@
msr_t msr;
int num_banks;
int msrno;
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
@@ -75,7 +75,7 @@
/* Enable the local CPU APICs */
setup_lapic();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index 6016751..ad4a7ea 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -19,7 +19,7 @@
#include <console/console.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
-#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
+#if CONFIG(HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
@@ -124,7 +124,7 @@
}
}
-#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
+#if (!CONFIG(CPU_AMD_MODEL_10XXX))
//it is running on core0 of node0
static void start_other_cores(void)
{
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
index 7788a2d..b2b915f 100644
--- a/src/cpu/intel/car/non-evict/cache_as_ram.S
+++ b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -134,7 +134,7 @@
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr
-#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR)
+#if CONFIG(CPU_HAS_L2_ENABLE_MSR)
/*
* Enable the L2 cache. Currently this assumes that this
* only affect socketed CPU's for which this is always valid,
@@ -152,7 +152,7 @@
invd
movl %eax, %cr0
-#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
+#if CONFIG(MICROCODE_UPDATE_PRE_RAM)
update_microcode:
/* put the return address in %esp */
movl $end_microcode_update, %esp
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 9d50582..4beac0b 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -23,7 +23,7 @@
/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/* Fixed location, ASSERTED in failover.ld if it changes. */
.set ap_sipi_vector_in_rom, 0xff
#endif
@@ -318,7 +318,7 @@
invd
movl %eax, %cr0
-#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
+#if CONFIG(MICROCODE_UPDATE_PRE_RAM)
update_microcode:
/* put the return address in %esp */
movl $end_microcode_update, %esp
diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
index 264ad4a..a7daff4 100644
--- a/src/cpu/intel/car/romstage.c
+++ b/src/cpu/intel/car/romstage.c
@@ -54,7 +54,7 @@
platform_enter_postcar();
}
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
* keeping changes in cache_as_ram.S easy to manage.
*/
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index a568ea1..a2ff65c 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -31,7 +31,7 @@
{
msr_t msr;
uint32_t feature_flag;
- int enable = IS_ENABLED(CONFIG_ENABLE_VMX);
+ int enable = CONFIG(ENABLE_VMX);
feature_flag = cpu_get_feature_flags_ecx();
/* Check that the VMX is supported before reading or writing the MSR. */
@@ -71,7 +71,7 @@
void set_feature_ctrl_lock(void)
{
msr_t msr;
- int lock = IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT);
+ int lock = CONFIG(SET_IA32_FC_LOCK_BIT);
uint32_t feature_flag = cpu_get_feature_flags_ecx();
/* Check if VMX is supported before reading or writing the MSR */
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
index 7994f0b..efa8693 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
@@ -132,7 +132,7 @@
x86_enable_cache();
/* Load microcode */
- if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+ if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
/* Clear out pending MCEs */
diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c
index 3a306b5..722cc01 100644
--- a/src/cpu/intel/haswell/bootblock.c
+++ b/src/cpu/intel/haswell/bootblock.c
@@ -23,7 +23,7 @@
#include <cpu/intel/microcode/microcode.c>
#include "haswell.h"
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)
+#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/lynxpoint/pch.h>
#else
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index d5028c2..1e5f3d3 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -30,7 +30,7 @@
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
-#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+#if CONFIG(EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#endif
#include <northbridge/intel/haswell/haswell.h>
@@ -89,7 +89,7 @@
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
if (wake_from_s3) {
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
@@ -131,7 +131,7 @@
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
- #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+ #if CONFIG(HAVE_ACPI_RESUME)
/* Failed S3 resume, reset to come up cleanly */
system_reset();
#endif
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index b05d3d4..f2f28f6 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -19,7 +19,7 @@
#include <smp/spinlock.h>
#include <assert.h>
-#if IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)
+#if CONFIG(PARALLEL_CPU_INIT)
#error Intel hyper-threading requires serialized CPU init
#endif
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index 48909c2..ea2d838 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -75,7 +75,7 @@
printk(BIOS_DEBUG, "SMRR status: %senabled\n",
ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
} else {
- if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT))
+ if (!CONFIG(SET_IA32_FC_LOCK_BIT))
printk(BIOS_INFO,
"Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n");
ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c
index ed528d1..19dbda8 100644
--- a/src/cpu/intel/model_2065x/bootblock.c
+++ b/src/cpu/intel/model_2065x/bootblock.c
@@ -23,7 +23,7 @@
#include <cpu/intel/microcode/microcode.c>
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)
+#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK)
#include <southbridge/intel/ibexpeak/pch.h>
#include "model_2065x.h"
#else
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 670b097..9dcbe37 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -24,8 +24,8 @@
#include <cpu/intel/microcode/microcode.c>
#include "model_206ax.h"
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) || \
- IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
+#if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \
+ CONFIG(SOUTHBRIDGE_INTEL_C216)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/bd82x6x/pch.h>
#else
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index fc0db17..d348df6 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -24,7 +24,7 @@
/* Turn on caching if we haven't already */
x86_enable_cache();
- if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
+ if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
@@ -37,7 +37,7 @@
setup_lapic();
/* Start up my CPU siblings */
- if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+ if (!CONFIG(PARALLEL_MP))
intel_sibling_init(cpu);
};
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 4b824a5..cc2a895 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -175,7 +175,7 @@
}
/* Adjust available SMM handler memory size. */
- if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
+ if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE);
params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
}
diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
index c31f4c0..12cbfc0 100644
--- a/src/cpu/intel/turbo/turbo.c
+++ b/src/cpu/intel/turbo/turbo.c
@@ -19,7 +19,7 @@
#include <cpu/x86/msr.h>
#include <arch/cpu.h>
-#if IS_ENABLED(CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)
+#if CONFIG(CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)
static inline int get_global_turbo_state(void)
{
return TURBO_UNKNOWN;
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 2a9f8c5..9e00c55 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -29,8 +29,8 @@
#include <arch/rom_segs.h>
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \
- IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \
+ CONFIG(SIPI_VECTOR_IN_ROM)
/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
* Startup IPI message without RAM.
*/
@@ -44,7 +44,7 @@
cli
/* Save the BIST result */
movl %eax, %ebp
-#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
+#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_RESET_VECTOR_CORRECT)
#endif
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 837bccf..52c0768 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -47,7 +47,7 @@
/* Save the BIST value */
movl %eax, %ebp
-#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
+#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_ENTER_PROTECTED_MODE)
#endif
diff --git a/src/cpu/x86/backup_default_smm.c b/src/cpu/x86/backup_default_smm.c
index 2023aed..7b982a6 100644
--- a/src/cpu/x86/backup_default_smm.c
+++ b/src/cpu/x86/backup_default_smm.c
@@ -25,7 +25,7 @@
void *save_area;
const void *default_smm = (void *)SMM_DEFAULT_BASE;
- if (!IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+ if (!CONFIG(HAVE_ACPI_RESUME))
return NULL;
/*
diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c
index 1a99c36..6fc6168 100644
--- a/src/cpu/x86/car.c
+++ b/src/cpu/x86/car.c
@@ -20,7 +20,7 @@
#include <arch/early_variables.h>
#include <symbols.h>
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
+#if CONFIG(PLATFORM_USES_FSP1_0)
#include <drivers/intel/fsp1_0/fsp_util.h>
#endif
typedef void (* const car_migration_func_t)(void);
@@ -61,7 +61,7 @@
return var;
}
-#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
+#if CONFIG(PLATFORM_USES_FSP1_0)
migrated_base = (char *)find_saved_temp_mem(
*(void **)CBMEM_FSP_HOB_PTR);
/* FSP 1.0 migrates the entire DCACHE RAM */
@@ -96,7 +96,7 @@
* keep console buffer in CAR until cbmemc_reinit() moves it.
*/
if (*mig_var == _preram_cbmem_console) {
- if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0))
+ if (CONFIG(PLATFORM_USES_FSP1_0))
*mig_var += (char *)mig_var - (char *)var;
return mig_var;
}
@@ -142,7 +142,7 @@
static void car_migrate_variables(int is_recovery)
{
- if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0))
+ if (!CONFIG(PLATFORM_USES_FSP1_0))
do_car_migrate_variables();
}
ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables)
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index ea10fd0..6521a8a 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -98,7 +98,7 @@
} while ((start - value) < ticks);
}
-#if IS_ENABLED(CONFIG_LAPIC_MONOTONIC_TIMER)
+#if CONFIG(LAPIC_MONOTONIC_TIMER)
#include <timer.h>
static struct monotonic_counter {
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 4654086..f4c2326 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -15,7 +15,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic_def.h>
-#if IS_ENABLED(CONFIG_SMP)
+#if CONFIG(SMP)
int boot_cpu(void)
{
int bsp;
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 7daca0a..3ad1f0a 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -147,9 +147,9 @@
}
return 0;
}
-#if !IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) \
- && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_206AX) \
- && !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_2065X)
+#if !CONFIG(CPU_AMD_MODEL_10XXX) \
+ && !CONFIG(CPU_INTEL_MODEL_206AX) \
+ && !CONFIG(CPU_INTEL_MODEL_2065X)
mdelay(10);
#endif
@@ -320,7 +320,7 @@
return result;
}
-#if IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT)
+#if CONFIG(AP_IN_SIPI_WAIT)
/**
* Sending INIT IPI to self is equivalent of asserting #INIT with a bit of
@@ -408,7 +408,7 @@
{
atomic_inc(&active_cpus);
- if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ if (!CONFIG(PARALLEL_CPU_INIT))
spin_lock(&start_cpu_lock);
#ifdef __SSE3__
@@ -423,7 +423,7 @@
#endif
cpu_initialize(index);
- if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ if (!CONFIG(PARALLEL_CPU_INIT))
spin_unlock(&start_cpu_lock);
atomic_dec(&active_cpus);
@@ -440,7 +440,7 @@
if (cpu->path.type != DEVICE_PATH_APIC)
continue;
- if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
+ if (CONFIG(PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
continue;
if (!cpu->enabled)
@@ -454,7 +454,7 @@
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
- if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ if (!CONFIG(PARALLEL_CPU_INIT))
udelay(10);
}
@@ -554,24 +554,24 @@
if (is_smp_boot())
copy_secondary_start_to_lowest_1M();
- if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))
+ if (!CONFIG(SERIALIZED_SMM_INITIALIZATION))
smm_init();
/* start all aps at first, so we can init ECC all together */
- if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ if (is_smp_boot() && CONFIG(PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);
/* Initialize the bootstrap processor */
cpu_initialize(0);
- if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
+ if (is_smp_boot() && !CONFIG(PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);
/* Now wait the rest of the cpus stop*/
if (is_smp_boot())
wait_other_cpus_stop(cpu_bus);
- if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) {
+ if (CONFIG(SERIALIZED_SMM_INITIALIZATION)) {
/* At this point, all APs are sleeping:
* smm_init() will queue a pending SMI on all cpus
* and smm_other_cpus() will start them one by one */
@@ -589,7 +589,7 @@
recover_lowest_1M();
}
-#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+#if !CONFIG(HAVE_SMI_HANDLER)
/* Empty stubs for platforms without SMI handlers. */
void smm_init(void)
{
diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
index 3889c7d..2057df0 100644
--- a/src/cpu/x86/mp_init.c
+++ b/src/cpu/x86/mp_init.c
@@ -714,7 +714,7 @@
static int is_smm_enabled(void)
{
- return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && mp_state.do_smm;
+ return CONFIG(HAVE_SMI_HANDLER) && mp_state.do_smm;
}
static void smm_disable(void)
@@ -724,7 +724,7 @@
static void smm_enable(void)
{
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
+ if (CONFIG(HAVE_SMI_HANDLER))
mp_state.do_smm = 1;
}
@@ -891,7 +891,7 @@
struct stopwatch sw;
int cur_cpu = cpu_index();
- if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) {
+ if (!CONFIG(PARALLEL_MP_AP_WORK)) {
printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n");
return -1;
}
@@ -933,7 +933,7 @@
struct mp_callback **per_cpu_slot;
int cur_cpu;
- if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK))
+ if (!CONFIG(PARALLEL_MP_AP_WORK))
return;
cur_cpu = cpu_index();
@@ -1028,7 +1028,7 @@
* Default to smm_initiate_relocation() if trigger callback isn't
* provided.
*/
- if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) &&
+ if (CONFIG(HAVE_SMI_HANDLER) &&
ops->per_cpu_smm_trigger == NULL)
mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation;
}
diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c
index c562d84..c430bc1 100644
--- a/src/cpu/x86/mtrr/debug.c
+++ b/src/cpu/x86/mtrr/debug.c
@@ -197,6 +197,6 @@
asmlinkage void display_mtrrs(void)
{
- if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
+ if (CONFIG(DISPLAY_MTRRS))
_display_mtrrs();
}
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index b45d17f..d87c3d4 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,7 +36,7 @@
#include <memrange.h>
#include <cpu/amd/mtrr.h>
#include <assert.h>
-#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
+#if CONFIG(X86_AMD_FIXED_MTRRS)
#define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM)
#else
#define MTRR_FIXED_WRBACK_BITS 0
@@ -86,7 +86,7 @@
{
msr_t syscfg;
- if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS))
+ if (!CONFIG(X86_AMD_FIXED_MTRRS))
return;
syscfg = rdmsr(SYSCFG_MSR);
@@ -98,7 +98,7 @@
{
msr_t syscfg;
- if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS))
+ if (!CONFIG(X86_AMD_FIXED_MTRRS))
return;
syscfg = rdmsr(SYSCFG_MSR);
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index a7e4522..11f0c24 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -172,7 +172,7 @@
test %ebx, %ebx
jz 1f
-#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
+#if CONFIG(X86_AMD_FIXED_MTRRS)
/* Allow modification of RdDram and WrDram bits */
mov $SYSCFG_MSR, %ecx
rdmsr
@@ -189,7 +189,7 @@
dec %ebx
jnz load_msr
-#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
+#if CONFIG(X86_AMD_FIXED_MTRRS)
mov $SYSCFG_MSR, %ecx
rdmsr
and $~SYSCFG_MSR_MtrrFixDramModEn, %eax
@@ -202,7 +202,7 @@
and $~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax
mov %eax, %cr0
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
/* Enable sse instructions. */
mov %cr4, %eax
orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index 8c65cbd..0ffa465 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -19,7 +19,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
#include <spi-generic.h>
#endif
@@ -186,7 +186,7 @@
/* Allow drivers to initialize variables in SMM context. */
if (do_driver_init) {
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
spi_init();
#endif
do_driver_init = 0;
diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c
index f9af965..0d9abc5 100644
--- a/src/cpu/x86/smm/smm_module_handler.c
+++ b/src/cpu/x86/smm/smm_module_handler.c
@@ -18,7 +18,7 @@
#include <cpu/x86/smm.h>
#include <rmodule.h>
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
#include <spi-generic.h>
#endif
@@ -161,7 +161,7 @@
/* Allow drivers to initialize variables in SMM context. */
if (do_driver_init) {
-#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
+#if CONFIG(SPI_FLASH_SMM)
spi_init();
#endif
do_driver_init = 0;
@@ -180,7 +180,7 @@
expected_canary);
// Don't die if we can't indicate an error.
- if (IS_ENABLED(CONFIG_DEBUG_SMI))
+ if (CONFIG(DEBUG_SMI))
die("SMM Handler caused a stack overflow\n");
}
diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c
index 6c16645..80b2c27 100644
--- a/src/cpu/x86/smm/smm_module_loader.c
+++ b/src/cpu/x86/smm/smm_module_loader.c
@@ -346,7 +346,7 @@
return -1;
/* Clear SMM region */
- if (IS_ENABLED(CONFIG_DEBUG_SMI))
+ if (CONFIG(DEBUG_SMI))
memset(smram, 0xcd, size);
total_stack_size = params->per_cpu_stack_size *
@@ -370,7 +370,7 @@
base += alignment_size;
}
- if (IS_ENABLED(CONFIG_SSE)) {
+ if (CONFIG(SSE)) {
fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks;
/* FXSAVE area below all the stacks stack. */
fxsave_area = params->stack_top;
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 06c7fa4..f586b35 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -77,7 +77,7 @@
#endif
.global smm_handler_start
smm_handler_start:
-#if IS_ENABLED(CONFIG_SMM_LAPIC_REMAP_MITIGATION)
+#if CONFIG(SMM_LAPIC_REMAP_MITIGATION)
/* Check if the LAPIC register block overlaps with SMM.
* This block needs to work without data accesses because they
* may be routed into the LAPIC register block.
@@ -139,7 +139,7 @@
/* This is an ugly hack, and we should find a way to read the CPU index
* without relying on the LAPIC ID.
*/
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)
+#if CONFIG(CPU_AMD_AGESA_FAMILY15_TN)
/* LAPIC IDs start from 0x10; map that to the proper core index */
subl $0x10, %ecx
#endif
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index fa49def..c282904 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -21,9 +21,9 @@
// can it be cleaned up so this include is not required?
// It's needed right now because we get our DEFAULT_PMBASE from
// here.
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)
+#if CONFIG(SOUTHBRIDGE_INTEL_I82801DX)
#include <southbridge/intel/i82801dx/i82801dx.h>
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)
+#elif CONFIG(SOUTHBRIDGE_INTEL_I82801IX)
#include <southbridge/intel/i82801ix/i82801ix.h>
#else
#error "Southbridge needs SMM handler support."
@@ -32,7 +32,7 @@
// ADDR32() macro
#include <arch/registers.h>
-#if IS_ENABLED(CONFIG_SMM_TSEG)
+#if CONFIG(SMM_TSEG)
#error "Don't use this file with TSEG."
#endif /* CONFIG_SMM_TSEG */
@@ -154,7 +154,7 @@
/* End of southbridge specific section. */
-#if IS_ENABLED(CONFIG_DEBUG_SMM_RELOCATION)
+#if CONFIG(DEBUG_SMM_RELOCATION)
/* print [SMM-x] so we can determine if CPUx went to SMM */
movw $CONFIG_TTYS0_BASE, %dx
mov $'[', %al
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index a589cdb..0784822 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -98,7 +98,7 @@
static unsigned long calibrate_tsc(void)
{
- if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+ if (CONFIG(TSC_CONSTANT_RATE))
return tsc_freq_mhz();
else
return calibrate_tsc_with_pit();
@@ -135,7 +135,7 @@
}
}
-#if IS_ENABLED(CONFIG_TSC_MONOTONIC_TIMER)
+#if CONFIG(TSC_MONOTONIC_TIMER)
#include <timer.h>
static struct monotonic_counter {