| ## SPDX-License-Identifier: GPL-2.0-only |
| |
| chip soc/intel/skylake |
| |
| register "deep_s5_enable_ac" = "0" |
| register "deep_s5_enable_dc" = "0" |
| register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" |
| |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route. i.e. If this route changes then the affected GPE |
| # offset bits also need to be changed. |
| register "gpe0_dw0" = "GPP_B" |
| register "gpe0_dw1" = "GPP_D" |
| register "gpe0_dw2" = "GPP_E" |
| |
| # FSP Configuration |
| register "DspEnable" = "1" |
| register "IoBufferOwnership" = "3" |
| register "ScsEmmcHs400Enabled" = "0" |
| register "SkipExtGfxScan" = "1" |
| |
| # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s |
| register "PmConfigSlpS3MinAssert" = "0x02" |
| |
| # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s |
| register "PmConfigSlpS4MinAssert" = "0x04" |
| |
| # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s |
| register "PmConfigSlpSusMinAssert" = "0x03" |
| |
| # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s |
| register "PmConfigSlpAMinAssert" = "0x03" |
| |
| register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| |
| # VR Settings Configuration for 4 Domains |
| #+----------------+-----------+-----------+-------------+----------+ |
| #| Domain/Setting | SA | IA | GT Unsliced | GT | |
| #+----------------+-----------+-----------+-------------+----------+ |
| #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| #| Psi3Enable | 1 | 1 | 1 | 1 | |
| #| Psi4Enable | 1 | 1 | 1 | 1 | |
| #| ImonSlope | 0 | 0 | 0 | 0 | |
| #| ImonOffset | 0 | 0 | 0 | 0 | |
| #| IccMax | 7A | 34A | 35A | 35A | |
| #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| #+----------------+-----------+-----------+-------------+----------+ |
| register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(4), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .icc_max = VR_CFG_AMP(7), |
| .voltage_limit = 1520, |
| }" |
| |
| register "domain_vr_config[VR_IA_CORE]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(5), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .icc_max = VR_CFG_AMP(34), |
| .voltage_limit = 1520, |
| }" |
| |
| register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(5), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .icc_max = VR_CFG_AMP(35), |
| .voltage_limit = 1520, |
| }" |
| |
| register "domain_vr_config[VR_GT_SLICED]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(5), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .icc_max = VR_CFG_AMP(35), |
| .voltage_limit = 1520, |
| }" |
| |
| # Enable x1 slot |
| register "PcieRpEnable[7]" = "1" |
| register "PcieRpClkReqSupport[7]" = "1" |
| register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 |
| |
| # Enable x4 slot |
| register "PcieRpEnable[8]" = "1" |
| register "PcieRpClkReqSupport[8]" = "1" |
| register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 |
| |
| # Enable Root port 6 and 13. |
| register "PcieRpEnable[5]" = "1" |
| register "PcieRpEnable[12]" = "1" |
| |
| # Enable CLKREQ# |
| register "PcieRpClkReqSupport[5]" = "1" |
| register "PcieRpClkReqSupport[12]" = "1" |
| |
| # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# |
| register "PcieRpClkReqNumber[5]" = "0" |
| register "PcieRpClkReqNumber[12]" = "1" |
| |
| # USB related |
| register "SsicPortEnable" = "1" |
| |
| register "usb2_ports" = "{ |
| [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ |
| [1] = USB2_PORT_MID(OC3), /* Touch Pad */ |
| [2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */ |
| [3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */ |
| [4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */ |
| [5] = USB2_PORT_MID(OC0), /* Front Panel */ |
| [6] = USB2_PORT_MID(OC0), /* Front Panel */ |
| [7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ |
| [8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ |
| [9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ |
| [10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ |
| [11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */ |
| [12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ |
| [13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ |
| }" |
| |
| register "usb3_ports" = "{ |
| [0] = USB3_PORT_DEFAULT(OC5), /* OTG */ |
| [1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */ |
| [2] = USB3_PORT_DEFAULT(OC3), /* Flex */ |
| [3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */ |
| [4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ |
| [5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ |
| [6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ |
| [7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ |
| [8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ |
| [9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ |
| }" |
| |
| register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V |
| |
| # Must leave UART0 enabled or SD/eMMC will not work as PCI |
| |
| register "SataSalpSupport" = "1" |
| register "SataPortsEnable" = "{ |
| [0] = 1, |
| [1] = 1, |
| [2] = 1, |
| [3] = 1, |
| [4] = 1, |
| [5] = 1, |
| [6] = 1, |
| [7] = 1, |
| }" |
| register "SerialIoDevMode" = "{ |
| [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| [PchSerialIoIndexSpi0] = PchSerialIoPci, |
| [PchSerialIoIndexSpi1] = PchSerialIoPci, |
| [PchSerialIoIndexUart0] = PchSerialIoPci, |
| [PchSerialIoIndexUart1] = PchSerialIoPci, |
| [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| }" |
| |
| # PL2 override 25W |
| register "power_limits_config" = "{ |
| .tdp_pl2_override = 25, |
| }" |
| |
| # Send an extra VR mailbox command for the PS4 exit issue |
| register "SendVrMbxCmd" = "2" |
| |
| # Use default SD card detect GPIO configuration |
| #register "sdcard_cd_gpio" = "GPP_A7" |
| |
| device cpu_cluster 0 on end |
| device domain 0 on |
| device pci 00.0 on end # Host Bridge |
| device pci 02.0 on end # Integrated Graphics Device |
| device pci 04.0 off end # SA thermal subsystem |
| device pci 14.0 on end # USB xHCI |
| device pci 14.1 off end # USB xDCI (OTG) |
| device pci 14.2 on end # Thermal Subsystem |
| device pci 15.0 on end # I2C #0 |
| device pci 15.1 on end # I2C #1 |
| device pci 15.2 on end # I2C #2 |
| device pci 15.3 on end # I2C #3 |
| device pci 16.0 on end # Management Engine Interface 1 |
| device pci 16.1 off end # Management Engine Interface 2 |
| device pci 16.2 off end # Management Engine IDE-R |
| device pci 16.3 off end # Management Engine KT Redirection |
| device pci 16.4 off end # Management Engine Interface 3 |
| device pci 17.0 on end # SATA |
| device pci 19.0 on end # UART #2 |
| device pci 19.1 on end # I2C #5 |
| device pci 19.2 on end # I2C #4 |
| device pci 1c.0 on end # PCI Express Port 1 |
| device pci 1c.1 off end # PCI Express Port 2 |
| device pci 1c.2 off end # PCI Express Port 3 |
| device pci 1c.3 off end # PCI Express Port 4 |
| device pci 1c.4 off end # PCI Express Port 5 |
| device pci 1c.5 off end # PCI Express Port 6 |
| device pci 1c.6 off end # PCI Express Port 7 |
| device pci 1c.7 off end # PCI Express Port 8 |
| device pci 1d.0 off end # PCI Express Port 9 |
| device pci 1d.1 off end # PCI Express Port 10 |
| device pci 1d.2 off end # PCI Express Port 11 |
| device pci 1d.3 off end # PCI Express Port 12 |
| device pci 1e.0 on end # UART #0 |
| device pci 1e.1 on end # UART #1 |
| device pci 1e.2 on end # GSPI #0 |
| device pci 1e.3 on end # GSPI #1 |
| device pci 1e.4 off end # eMMC |
| device pci 1e.5 off end # SDIO |
| device pci 1e.6 off end # SDCard |
| device pci 1f.0 on |
| end # LPC Interface |
| device pci 1f.1 on end # P2SB |
| device pci 1f.2 on end # Power Management Controller |
| device pci 1f.3 on end # Intel HDA |
| device pci 1f.4 on end # SMBus |
| device pci 1f.5 on end # PCH SPI |
| device pci 1f.6 on end # GbE |
| end |
| end |