soc/amd,intel: Drop s3_resume parameter on FSP-S functions
ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.
Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index c7e3fb8..95ad865 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -10,7 +10,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -134,7 +133,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 9fab277..32f5ea2 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -19,7 +19,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -27,7 +26,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 39d9be5..7172231 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -23,7 +23,6 @@
#include <intelblocks/gpio.h>
#include <intelblocks/itss.h>
#include <intelblocks/pmclib.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/heci.h>
#include <soc/intel/common/vbt.h>
@@ -302,7 +301,7 @@
*/
gpi_clear_int_cfg();
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 0ae170b..a071337 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -24,7 +24,6 @@
#include <intelblocks/msr.h>
#include <intelblocks/sgx.h>
#include <reg_script.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
@@ -140,7 +139,7 @@
static void pre_mp_init(void)
{
if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) {
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
return;
}
x86_setup_mtrrs_with_detect();
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0958aac..4f467a1 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -10,7 +10,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
@@ -171,7 +170,7 @@
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index f4b72ab..6a4f773 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -10,7 +10,6 @@
#include <cpu/intel/turbo.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -23,7 +22,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c
index 9cf3bfb..77ad8e7 100644
--- a/src/soc/intel/denverton_ns/chip.c
+++ b/src/soc/intel/denverton_ns/chip.c
@@ -43,7 +43,7 @@
static void soc_init(void *data)
{
- fsp_silicon_init(false);
+ fsp_silicon_init();
soc_save_dimm_info();
}
diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c
index 359aa11..001a6e1 100644
--- a/src/soc/intel/elkhartlake/chip.c
+++ b/src/soc/intel/elkhartlake/chip.c
@@ -10,7 +10,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -122,7 +121,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index d0fa019..984f7f2 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -13,7 +13,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -21,7 +20,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c
index d493f81..134d7cf 100644
--- a/src/soc/intel/icelake/chip.c
+++ b/src/soc/intel/icelake/chip.c
@@ -9,7 +9,6 @@
#include <intelblocks/gpio.h>
#include <intelblocks/itss.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -112,7 +111,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index 1734ba6..dd70c85 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -13,7 +13,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -21,7 +20,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index 1f58f84c..ce4004d 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -10,7 +10,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -128,7 +127,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 6518945..a3790e1 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -13,7 +13,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -21,7 +20,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 33033a9..e613ced 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -2,7 +2,6 @@
#include <assert.h>
#include <device/device.h>
-#include <romstage_handoff.h>
#include <soc/ramstage.h>
#include <soc/reg_access.h>
@@ -103,7 +102,7 @@
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
}
static struct device_operations pci_domain_ops = {
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index cb0fa2a..4f120bc 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -18,7 +18,6 @@
#include <intelblocks/xdci.h>
#include <intelblocks/p2sb.h>
#include <intelpch/lockdown.h>
-#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/intel/common/vbt.h>
#include <soc/interrupt.h>
@@ -56,7 +55,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/*
* Keep the P2SB device visible so it and the other devices are
@@ -77,7 +76,7 @@
void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static struct device_operations pci_domain_ops = {
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index f07cc58..8be04b6 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -11,7 +11,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -134,7 +133,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index 36dfa1b..974401f 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -19,7 +19,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -27,7 +26,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 778d277..2c731da 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -91,7 +91,7 @@
static void chip_init(void *data)
{
printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
- fsp_silicon_init(false);
+ fsp_silicon_init();
override_hpet_ioapic_bdf();
pch_enable_ioapic();
pch_lock_dmictl();
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index 4d50a25..92f2afa 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -59,7 +59,7 @@
static void soc_init(void *data)
{
printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
- fsp_silicon_init(false);
+ fsp_silicon_init();
override_hpet_ioapic_bdf();
pch_lock_dmictl();
}