soc/amd,intel: Drop s3_resume parameter on FSP-S functions
ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.
Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
index dec2393..d1b803e 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
@@ -8,7 +8,6 @@
/* Perform Intel silicon init. */
void intel_silicon_init(void);
-void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);
/* Called after the silicon init code has run. */
void soc_after_silicon_init(void);
/* Initialize UPD data before SiliconInit call. */
diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
index 34eec6e..22d4f1c 100644
--- a/src/drivers/intel/fsp1_1/ramstage.c
+++ b/src/drivers/intel/fsp1_1/ramstage.c
@@ -51,7 +51,7 @@
}
}
-void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
+static void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header)
{
FSP_SILICON_INIT fsp_silicon_init;
SILICON_INIT_UPD *original_params;
@@ -179,7 +179,7 @@
void intel_silicon_init(void)
{
fsp_load();
- fsp_run_silicon_init(fsp_get_fih(), acpi_is_wakeup_s3());
+ fsp_run_silicon_init(fsp_get_fih());
}
/* Initialize the UPD parameters for SiliconInit */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 63018c5..8561600 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -33,7 +33,7 @@
/* Main FSP stages */
void fsp_memory_init(bool s3wake);
-void fsp_silicon_init(bool s3wake);
+void fsp_silicon_init(void);
void fsp_temp_ram_exit(void);
/*
@@ -41,7 +41,7 @@
* separately from calling silicon init. It might be required in cases where
* stage cache is no longer available by the point SoC calls into silicon init.
*/
-void fsps_load(bool s3wake);
+void fsps_load(void);
/* Callbacks for updating stage-specific parameters */
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 270a872..6a2a73d 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -191,7 +191,7 @@
return 0;
}
-void fsps_load(bool s3wake)
+void fsps_load(void)
{
struct fsp_load_descriptor fspld = {
.fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_S_CBFS),
@@ -220,9 +220,9 @@
load_done = 1;
}
-void fsp_silicon_init(bool s3wake)
+void fsp_silicon_init(void)
{
- fsps_load(s3wake);
+ fsps_load();
do_silicon_init(&fsps_hdr);
}
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index f6cac14..accd3e9 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <device/device.h>
#include <fsp/api.h>
#include <soc/southbridge.h>
@@ -27,7 +26,7 @@
static void soc_init(void *chip_info)
{
- fsp_silicon_init(acpi_is_wakeup_s3());
+ fsp_silicon_init();
fch_init(chip_info);
}
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 17c7bd5..8722d57 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -102,7 +101,7 @@
{
default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
- fsp_silicon_init(acpi_is_wakeup_s3());
+ fsp_silicon_init();
data_fabric_set_mmio_np();
fch_init(chip_info);
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c
index c7e3fb8..95ad865 100644
--- a/src/soc/intel/alderlake/chip.c
+++ b/src/soc/intel/alderlake/chip.c
@@ -10,7 +10,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -134,7 +133,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 9fab277..32f5ea2 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -19,7 +19,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -27,7 +26,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 39d9be5..7172231 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -23,7 +23,6 @@
#include <intelblocks/gpio.h>
#include <intelblocks/itss.h>
#include <intelblocks/pmclib.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/heci.h>
#include <soc/intel/common/vbt.h>
@@ -302,7 +301,7 @@
*/
gpi_clear_int_cfg();
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Restore GPIO IRQ polarities back to previous settings. */
itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 0ae170b..a071337 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -24,7 +24,6 @@
#include <intelblocks/msr.h>
#include <intelblocks/sgx.h>
#include <reg_script.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
@@ -140,7 +139,7 @@
static void pre_mp_init(void)
{
if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) {
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
return;
}
x86_setup_mtrrs_with_detect();
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0958aac..4f467a1 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -10,7 +10,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
@@ -171,7 +170,7 @@
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c
index f4b72ab..6a4f773 100644
--- a/src/soc/intel/cannonlake/cpu.c
+++ b/src/soc/intel/cannonlake/cpu.c
@@ -10,7 +10,6 @@
#include <cpu/intel/turbo.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -23,7 +22,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c
index 9cf3bfb..77ad8e7 100644
--- a/src/soc/intel/denverton_ns/chip.c
+++ b/src/soc/intel/denverton_ns/chip.c
@@ -43,7 +43,7 @@
static void soc_init(void *data)
{
- fsp_silicon_init(false);
+ fsp_silicon_init();
soc_save_dimm_info();
}
diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c
index 359aa11..001a6e1 100644
--- a/src/soc/intel/elkhartlake/chip.c
+++ b/src/soc/intel/elkhartlake/chip.c
@@ -10,7 +10,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -122,7 +121,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c
index d0fa019..984f7f2 100644
--- a/src/soc/intel/elkhartlake/cpu.c
+++ b/src/soc/intel/elkhartlake/cpu.c
@@ -13,7 +13,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -21,7 +20,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c
index d493f81..134d7cf 100644
--- a/src/soc/intel/icelake/chip.c
+++ b/src/soc/intel/icelake/chip.c
@@ -9,7 +9,6 @@
#include <intelblocks/gpio.h>
#include <intelblocks/itss.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -112,7 +111,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c
index 1734ba6..dd70c85 100644
--- a/src/soc/intel/icelake/cpu.c
+++ b/src/soc/intel/icelake/cpu.c
@@ -13,7 +13,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -21,7 +20,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index 1f58f84c..ce4004d 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -10,7 +10,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -128,7 +127,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c
index 6518945..a3790e1 100644
--- a/src/soc/intel/jasperlake/cpu.c
+++ b/src/soc/intel/jasperlake/cpu.c
@@ -13,7 +13,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -21,7 +20,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c
index 33033a9..e613ced 100644
--- a/src/soc/intel/quark/chip.c
+++ b/src/soc/intel/quark/chip.c
@@ -2,7 +2,6 @@
#include <assert.h>
#include <device/device.h>
-#include <romstage_handoff.h>
#include <soc/ramstage.h>
#include <soc/reg_access.h>
@@ -103,7 +102,7 @@
| TS_LOCK_AUX_TRIP_PT_REGS_ENABLE));
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
}
static struct device_operations pci_domain_ops = {
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index cb0fa2a..4f120bc 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -18,7 +18,6 @@
#include <intelblocks/xdci.h>
#include <intelblocks/p2sb.h>
#include <intelpch/lockdown.h>
-#include <romstage_handoff.h>
#include <soc/acpi.h>
#include <soc/intel/common/vbt.h>
#include <soc/interrupt.h>
@@ -56,7 +55,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/*
* Keep the P2SB device visible so it and the other devices are
@@ -77,7 +76,7 @@
void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static struct device_operations pci_domain_ops = {
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index f07cc58..8be04b6 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -11,7 +11,6 @@
#include <intelblocks/itss.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/xdci.h>
-#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/pci_devs.h>
@@ -134,7 +133,7 @@
itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
/* Perform silicon specific init. */
- fsp_silicon_init(romstage_handoff_is_resume());
+ fsp_silicon_init();
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index 36dfa1b..974401f 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -19,7 +19,6 @@
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/msr.h>
-#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -27,7 +26,7 @@
static void soc_fsp_load(void)
{
- fsps_load(romstage_handoff_is_resume());
+ fsps_load();
}
static void configure_misc(void)
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 778d277..2c731da 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -91,7 +91,7 @@
static void chip_init(void *data)
{
printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
- fsp_silicon_init(false);
+ fsp_silicon_init();
override_hpet_ioapic_bdf();
pch_enable_ioapic();
pch_lock_dmictl();
diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c
index 4d50a25..92f2afa 100644
--- a/src/soc/intel/xeon_sp/skx/chip.c
+++ b/src/soc/intel/xeon_sp/skx/chip.c
@@ -59,7 +59,7 @@
static void soc_init(void *data)
{
printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
- fsp_silicon_init(false);
+ fsp_silicon_init();
override_hpet_ioapic_bdf();
pch_lock_dmictl();
}