| chip soc/intel/alderlake |
| # Intel Common SoC Config |
| #+-------------------+---------------------------+ |
| #| Field | Value | |
| #+-------------------+---------------------------+ |
| #| I2C0 | Audio | |
| #| I2C1 | GPU | |
| #| I2C2 | External graphic | |
| #| I2C3 | cr50 TPM. Early init is | |
| #| | required to set up a BAR | |
| #| | for TPM communication | |
| #| I2C5 | Trackpad | |
| #+-------------------+---------------------------+ |
| register "common_soc_config" = "{ |
| .i2c[0] = { |
| .speed = I2C_SPEED_FAST, |
| }, |
| .i2c[1] = { |
| .speed = I2C_SPEED_FAST, |
| }, |
| .i2c[2] = { |
| .speed = I2C_SPEED_FAST, |
| }, |
| .i2c[3] = { |
| .early_init = 1, |
| .speed = I2C_SPEED_FAST, |
| }, |
| .i2c[5] = { |
| .speed = I2C_SPEED_FAST, |
| }, |
| }" |
| |
| register "sagv" = "SaGv_Enabled" |
| register "tcss_aux_ori" = "0x10" |
| register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" |
| |
| register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 |
| register "usb2_ports[2]" = "USB2_PORT_MAX_TYPE_C(OC2)" # set to Max for USB2_C2 |
| register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN |
| register "usb2_ports[4]" = "USB2_PORT_EMPTY" # |
| register "usb2_ports[6]" = "USB2_PORT_EMPTY" # |
| register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 |
| |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A2 |
| register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable M.2 WWAN |
| |
| register "serial_io_i2c_mode" = "{ |
| [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| [PchSerialIoIndexI2C2] = PchSerialIoPci, |
| [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| }" |
| |
| register "serial_io_gspi_mode" = "{ |
| [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, |
| [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |
| }" |
| |
| device domain 0 on |
| device ref pcie4_0 on |
| # Enable CPU PCIe RP 1 using CLKREQ 0 and CLKSRC 0 |
| register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| .clk_req = 0, |
| .clk_src = 0, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| device pci 00.0 alias dgpu on end |
| end |
| device ref dtt on |
| chip drivers/intel/dptf |
| ## sensor information |
| register "options.tsr[0].desc" = ""DRAM"" |
| register "options.tsr[1].desc" = ""Soc"" |
| register "options.tsr[2].desc" = ""Charger"" |
| register "options.tsr[3].desc" = ""Regulator"" |
| # TODO: below values are initial reference values only |
| ## Passive Policy |
| register "policies.passive" = "{ |
| [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), |
| [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), |
| [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), |
| [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), |
| [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000), |
| }" |
| ## Critical Policy |
| register "policies.critical" = "{ |
| [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), |
| [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), |
| [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), |
| [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), |
| [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), |
| }" |
| register "controls.power_limits" = "{ |
| .pl1 = { |
| .min_power = 3000, |
| .max_power = 15000, |
| .time_window_min = 28 * MSECS_PER_SEC, |
| .time_window_max = 32 * MSECS_PER_SEC, |
| .granularity = 200, |
| }, |
| .pl2 = { |
| .min_power = 55000, |
| .max_power = 55000, |
| .time_window_min = 28 * MSECS_PER_SEC, |
| .time_window_max = 32 * MSECS_PER_SEC, |
| .granularity = 1000, |
| } |
| }" |
| ## Charger Performance Control (Control, mA) |
| register "controls.charger_perf" = "{ |
| [0] = { 255, 1700 }, |
| [1] = { 24, 1500 }, |
| [2] = { 16, 1000 }, |
| [3] = { 8, 500 } |
| }" |
| device generic 0 on end |
| end |
| end |
| device ref cnvi_wifi on |
| chip drivers/wifi/generic |
| register "wake" = "GPE0_PME_B0" |
| device generic 0 on end |
| end |
| end |
| device ref i2c0 on |
| chip drivers/i2c/generic |
| register "hid" = ""RTL5682"" |
| register "name" = ""RT58"" |
| register "desc" = ""Headset Codec"" |
| register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" |
| # Set the jd_src to RT5668_JD1 for jack detection |
| register "property_count" = "1" |
| register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| register "property_list[0].name" = ""realtek,jd-src"" |
| register "property_list[0].integer" = "1" |
| device i2c 1a on end |
| end |
| end #I2C0 |
| device ref i2c1 on end # GPU |
| device ref i2c2 on end # External GPU |
| device ref i2c3 on |
| chip drivers/i2c/tpm |
| register "hid" = ""GOOG0005"" |
| register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" |
| device i2c 50 on end |
| end |
| end |
| device ref i2c5 on |
| chip drivers/i2c/generic |
| register "hid" = ""ELAN0000"" |
| register "desc" = ""ELAN Touchpad"" |
| register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" |
| register "wake" = "GPE0_DW2_14" |
| register "probed" = "1" |
| device i2c 15 on end |
| end |
| end |
| device ref pcie_rp3 on |
| # Enable PCIE 3 using clk 4 |
| register "pch_pcie_rp[PCH_RP(3)]" = "{ |
| .clk_src = 4, |
| .clk_req = 4, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| chip drivers/net |
| register "customized_leds" = "0x05af" |
| register "wake" = "GPE0_DW0_07" |
| register "device_index" = "0" |
| device pci 00.0 on end |
| end |
| end #RTL8111H Ethernet NIC |
| device ref pcie_rp4 off end |
| device ref pcie_rp6 off end |
| device ref pcie_rp7 off end |
| device ref pcie_rp8 on |
| chip soc/intel/common/block/pcie/rtd3 |
| register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" |
| register "srcclk_pin" = "3" |
| device generic 0 on end |
| end |
| end #PCIE8 SD card |
| device ref hda on |
| chip drivers/generic/max98357a |
| register "hid" = ""MX98360A"" |
| register "sdmode_gpio" = |
| "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" |
| register "sdmode_delay" = "5" |
| device generic 0 on end |
| end |
| end |
| device ref pch_espi on |
| chip ec/google/chromeec |
| use conn0 as mux_conn[0] |
| use conn1 as mux_conn[1] |
| device pnp 0c09.0 on end |
| end |
| end |
| device ref pmc hidden |
| chip drivers/intel/pmc_mux |
| device generic 0 on |
| chip drivers/intel/pmc_mux/conn |
| use usb2_port1 as usb2_port |
| use tcss_usb3_port3 as usb3_port |
| device generic 0 alias conn0 on end |
| end |
| chip drivers/intel/pmc_mux/conn |
| use usb2_port3 as usb2_port |
| use tcss_usb3_port1 as usb3_port |
| device generic 1 alias conn1 on end |
| end |
| end |
| end |
| end |
| device ref tcss_xhci on |
| chip drivers/usb/acpi |
| device ref tcss_root_hub on |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-C Port C0 (MLB)"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" |
| device ref tcss_usb3_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-C Port C2 (MLB)"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" |
| device ref tcss_usb3_port3 on end |
| end |
| end |
| end |
| end |
| device ref xhci on |
| chip drivers/usb/acpi |
| device ref xhci_root_hub on |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-C Port C0 (MLB)"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" |
| device ref usb2_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-C Port C2 (MLB)"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" |
| device ref usb2_port3 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Camera"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device ref usb2_port6 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Port 2"" |
| register "type" = "UPC_TYPE_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 2))" |
| device ref usb2_port8 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Port 0"" |
| register "type" = "UPC_TYPE_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" |
| device ref usb2_port9 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Bluetooth"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| register "reset_gpio" = |
| "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" |
| device ref usb2_port10 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-A Port 0"" |
| register "type" = "UPC_TYPE_USB3_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" |
| device ref usb3_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-A Port 2"" |
| register "type" = "UPC_TYPE_USB3_A" |
| register "use_custom_pld" = "true" |
| register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 2))" |
| device ref usb3_port2 on end |
| end |
| end |
| end |
| end |
| end |
| end |