superio/ite: Add IT8629E
Unfortunately, the datasheet for IT8629E is not public. Therefore, we
will use the functionally closest chip (i.e. IT8728F) as a reference
and try to reverse-engineer where necessary.
IT8629E seems to be very similar to IT8628E (again, no public
datasheets), as the chip id is 0x8628.
Known differences:
- LDN 0x08 (functionality is unknown)
- Supports 6 fans
Change-Id: I44d0377da11f0e118017caa4357012df9373b322
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80344
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/superio/ite/Makefile.mk b/src/superio/ite/Makefile.mk
index 23d86da..b6d0199 100644
--- a/src/superio/ite/Makefile.mk
+++ b/src/superio/ite/Makefile.mk
@@ -10,6 +10,7 @@
subdirs-y += it8528e
subdirs-y += it8613e
subdirs-y += it8623e
+subdirs-y += it8629e
subdirs-y += it8712f
subdirs-y += it8718f
subdirs-y += it8720f
diff --git a/src/superio/ite/it8629e/Kconfig b/src/superio/ite/it8629e/Kconfig
new file mode 100644
index 0000000..29e72b6
--- /dev/null
+++ b/src/superio/ite/it8629e/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config SUPERIO_ITE_IT8629E
+ bool
+ select SUPERIO_ITE_COMMON_PRE_RAM
+ select SUPERIO_ITE_ENV_CTRL
+ select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2
+ select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG
+ select SUPERIO_ITE_ENV_CTRL_8BIT_PWM
+ select SUPERIO_ITE_ENV_CTRL_5FANS # TODO: Add support for 6 fans
+ select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG
+ select SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN
diff --git a/src/superio/ite/it8629e/Makefile.mk b/src/superio/ite/it8629e/Makefile.mk
new file mode 100644
index 0000000..c574158
--- /dev/null
+++ b/src/superio/ite/it8629e/Makefile.mk
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8629E) += superio.c
diff --git a/src/superio/ite/it8629e/chip.h b/src/superio/ite/it8629e/chip.h
new file mode 100644
index 0000000..bad0266
--- /dev/null
+++ b/src/superio/ite/it8629e/chip.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_ITE_IT8629E_CHIP_H
+#define SUPERIO_ITE_IT8629E_CHIP_H
+
+#include <superio/ite/common/env_ctrl_chip.h>
+
+struct superio_ite_it8629e_config {
+ struct ite_ec_config ec;
+};
+
+#endif /* SUPERIO_ITE_IT8629E_CHIP_H */
diff --git a/src/superio/ite/it8629e/it8629e.h b/src/superio/ite/it8629e/it8629e.h
new file mode 100644
index 0000000..573ca28
--- /dev/null
+++ b/src/superio/ite/it8629e/it8629e.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SUPERIO_ITE_IT8629E_H
+#define SUPERIO_ITE_IT8629E_H
+
+#define IT8629E_FDC 0x00 // FDC
+#define IT8629E_SP1 0x01 // Serial Port 1
+#define IT8629E_SP2 0x02 // Serial Port 2
+#define IT8629E_PP 0x03 // Parallel Port
+#define IT8629E_EC 0x04 // Environment Controller
+#define IT8629E_KBCK 0x05 // PS/2 Keyboard
+#define IT8629E_KBCM 0x06 // PS/2 Mouse
+#define IT8629E_GPIO 0x07 // GPIO
+#define IT8629E_UNKNOWN 0x08
+#define IT8629E_IR 0x0a // Consumer IR
+
+#endif /* SUPERIO_ITE_IT8629E_H */
diff --git a/src/superio/ite/it8629e/superio.c b/src/superio/ite/it8629e/superio.c
new file mode 100644
index 0000000..51f7c22
--- /dev/null
+++ b/src/superio/ite/it8629e/superio.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <superio/conf_mode.h>
+#include <pc80/keyboard.h>
+#include <superio/ite/common/env_ctrl.h>
+
+#include "chip.h"
+#include "it8629e.h"
+
+static void it8629e_init(struct device *dev)
+{
+ const struct superio_ite_it8629e_config *conf = dev->chip_info;
+ const struct resource *res;
+
+ if (!dev->enabled)
+ return;
+
+ switch (dev->path.pnp.device) {
+ /* TODO: Might potentially need code for FDC etc. */
+ case IT8629E_EC:
+ res = probe_resource(dev, PNP_IDX_IO0);
+ if (!conf || !res)
+ break;
+ ite_ec_init(res->base, &conf->ec);
+ break;
+ case IT8629E_KBCK:
+ set_kbc_ps2_mode();
+ pc_keyboard_init(NO_AUX_DEVICE);
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = it8629e_init,
+ .ops_pnp_mode = &pnp_conf_mode_870155_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { NULL, IT8629E_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ff8, },
+ { NULL, IT8629E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8629E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+ { NULL, IT8629E_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, 0x0ffc, },
+ { NULL, IT8629E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0ff8, 0x0ff8, },
+ { NULL, IT8629E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x0fff, 0x0fff, },
+ { NULL, IT8629E_KBCM, PNP_IRQ0, },
+ { NULL, IT8629E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0,
+ 0x0fff, 0x0ff8, 0x0ff8, },
+ { NULL, IT8629E_UNKNOWN, PNP_IO0 | PNP_IRQ0, 0xff8, },
+ { NULL, IT8629E_IR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8629e_ops = {
+ .name = "ITE IT8629E Super I/O",
+ .enable_dev = enable_dev
+};