sb/intel/i82801jx: Fix 16-bit read/write PCI_COMMAND register
Change-Id: If39cdfb21fec307141593f2482e014e146d4f1f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index dba1a65..df3140a 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -20,9 +20,7 @@
printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n");
/* Enable Bus Master */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 |= PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it